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Tom Gardner
Guest

Tue Jan 08, 2019 10:45 am   



On 08/01/19 00:25, Phil Hobbs wrote:
Quote:
On 1/6/19 5:58 PM, Tom Gardner wrote:
On 06/01/19 20:36, Lasse Langwadt Christensen wrote:
søndag den 6. januar 2019 kl. 21.22.28 UTC+1 skrev Tom Gardner:
On 06/01/19 19:45, Lasse Langwadt Christensen wrote:
søndag den 6. januar 2019 kl. 20.38.57 UTC+1 skrev Tom Gardner:
On 06/01/19 14:05, Kevin Aylward wrote:
The vast majority of patents are worthless. Big companies don't care how
much
they lose in getting patents for obvious ideas. They are just sticks to
threaten
people with.

As I'm sure you are aware, there are five principal
reasons to get a patent:
    1 an egoboost or career boost
    2 to profit from the invention being used by others
    3 so investors in a company have something "tangible"
      to sell to another investor
    4 pile 'em high patent portfolio swaps
    5 to prevent other people patenting it and stopping you
      from exploiting your invention

Some are more justifiable than others, and there
are cheaper ways to achieve the last one.

isn't five covered by selling stuff? i.e. if you can prove you have sold
something that does what someone later tries to patent it is considered
prior art and can't be patented

IANAL, but the essence of patents is disclosure
of the techniques involved. I doubt simply selling
an item is sufficient. OTOH publishing a technique
certainly is sufficient, and is much cheaper.

I believe there are publications regarded as
normal channels for that. I doubt anyone reads
them, so it might be considered "security
through obscurity".

IANAL either but,

https://www.iusmentis.com/patents/priorart/

Indeed, provided the invention is, in some way
or other, demonstrably visible. That can be
very difficult to prove, especially with
"invisible" embedded software.

When there are hundreds of millions of dollars at stake, you'd be surprised at
what you can get done.


Undoubtedly true. Such money can be used in a variety
of ways, of course.

Phil Hobbs
Guest

Tue Jan 08, 2019 5:45 pm   



On 1/8/19 4:29 AM, Tom Gardner wrote:
Quote:
On 08/01/19 00:25, Phil Hobbs wrote:
On 1/6/19 5:58 PM, Tom Gardner wrote:
On 06/01/19 20:36, Lasse Langwadt Christensen wrote:
søndag den 6. januar 2019 kl. 21.22.28 UTC+1 skrev Tom Gardner:
On 06/01/19 19:45, Lasse Langwadt Christensen wrote:
søndag den 6. januar 2019 kl. 20.38.57 UTC+1 skrev Tom Gardner:
On 06/01/19 14:05, Kevin Aylward wrote:
The vast majority of patents are worthless. Big companies don't
care how much
they lose in getting patents for obvious ideas. They are just
sticks to threaten
people with.

As I'm sure you are aware, there are five principal
reasons to get a patent:
    1 an egoboost or career boost
    2 to profit from the invention being used by others
    3 so investors in a company have something "tangible"
      to sell to another investor
    4 pile 'em high patent portfolio swaps
    5 to prevent other people patenting it and stopping you
      from exploiting your invention

Some are more justifiable than others, and there
are cheaper ways to achieve the last one.

isn't five covered by selling stuff? i.e. if you can prove you
have sold
something that does what someone later tries to patent it is
considered
prior art and can't be patented

IANAL, but the essence of patents is disclosure
of the techniques involved. I doubt simply selling
an item is sufficient. OTOH publishing a technique
certainly is sufficient, and is much cheaper.

I believe there are publications regarded as
normal channels for that. I doubt anyone reads
them, so it might be considered "security
through obscurity".

IANAL either but,

https://www.iusmentis.com/patents/priorart/

Indeed, provided the invention is, in some way
or other, demonstrably visible. That can be
very difficult to prove, especially with
"invisible" embedded software.

When there are hundreds of millions of dollars at stake, you'd be
surprised at what you can get done.

Undoubtedly true. Such money can be used in a variety
of ways, of course.


One is to have a reverse-engineering firm give you transistor-level
schematics and read out the flash to get the binary.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
https://hobbs-eo.com

Kevin Aylward
Guest

Mon Jan 14, 2019 9:45 pm   



Quote:
"Gerhard Hoffmann" wrote in message
news:g9caliF73srU1_at_mid.individual.net...


But if you controlled the sustaining current more carefully you wouldn't
need a limiter.

This is not the limiting of the oscillator, it is the squaring up
*comparator* that converts the sine wave to rectangle. Its mandatory. to
have a square wave output. The oscillator amplitude limiting to have the
gain equal to one is a different issue.

That is not exactly big news.

Oliver Collins: The design of low jitter hard limiters
https://ieeexplore.ieee.org/document/494304


Quote:
(I have seen it outside of the IEEE Wall Of Shame in the wilderness
of the internet.)


I have not located a copy yet. However, I have found references that
discuss it.

http://www.ko4bb.com/~bruce/ZeroCrossingDetectors.html

which references this:

http://www.ko4bb.com/~bruce/GeneralisedCollinsHardLimiterPaperV3B.pdf

It is clear that little understanding of *practical*, current commercial
design is
shown in the approach. I can say its useless for xtal oscillator limiters,
just from reading the above paper. It shows no appreciation of how the
amplifies and filters are actually constructed for starters. The fundamental
issue is, how is an amplifier designed such that its supply current is
minimised whilst minimising the noise. The topology is the bit that actually
counts.

I can't stress this enough. It is the solving for optimum noise/current that
is crucial. Anyone can get low noise if they have 1 amp available.

A key bit is the filtering noise standard of a xtal oscillator is referenced
to a Q of say 100,000. It is impossible to filter to this level in
subsequent gain stages. In an ASIC going into a 5mm x 7mm or 3mm x 5mm
package, inductor filters are just not an option. So, its simply not
possible to put meaningful filtering between gain stages for high
performance systems


>https://people.mpi-inf.mpg.de/~adogan/pubs/IFCS2018_comparator_noise.pdf

These mathematical approaches are completely worthless for real, commercial
design. For starters, the waveforms are just too nonlinear to model with
approximations.

Optimum phase noise osc/amp design today is done, essentially, with no user
mathematics whatsoever. Its done by understanding qualitivity what the
physical noise mechanisms are, are running PSS/PNOISE simulations with
software tools that just spits out the results.

>>And the LTC6957 family is also not bad.

Its not that good either.

It quotes around -161 dBc flat band noise at a supply current of 15 mA.

For the topology I developed for my ASICS, under the same operating
conditions as above, I would get typically -168 dBc at 2.2 mA. If I were to
adjust the design for 15 mA, it would be something like -176 dBc, at 5 times
lower noise.

I might post how its done, because quite frankly, after the fact, it is
truly, truly trivial, zero chance of being patented, the topology is already
used in
billions and billions of products for other purposes, but apparently not in
the LTC6957
et al.

What I will say though is that, as per the above paper actually analysing
the effects of clamping diodes, that clamping diodes are a disaster. They
may well be used to say, prevent a bipolar gain stage saturating but they
throw away supply current, which is the key bit we are trying to minimise.

That should be enough to figure what topology is truly the best.


-- Kevin Aylward
http://www.anasoft.co.uk - SuperSpice
http://www.kevinaylward.co.uk/ee/index.html

Joseph Gwinn
Guest

Tue Jan 15, 2019 4:45 am   



On Jan 14, 2019, Kevin Aylward wrote
(in article<FMadnTn488qibKHBnZ2dnUU7-cPNnZ2d_at_giganews.com>):

Quote:
"Gerhard Hoffmann" wrote in message
news:g9caliF73srU1_at_mid.individual.net...


But if you controlled the sustaining current more carefully you wouldn't
need a limiter.

This is not the limiting of the oscillator, it is the squaring up
*comparator* that converts the sine wave to rectangle. Its mandatory. to
have a square wave output. The oscillator amplitude limiting to have the
gain equal to one is a different issue.

That is not exactly big news.

Oliver Collins: The design of low jitter hard limiters
https://ieeexplore.ieee.org/document/494304

(I have seen it outside of the IEEE Wall Of Shame in the wilderness
of the internet.)

I have not located a copy yet. However, I have found references that
discuss it.

http://www.ko4bb.com/~bruce/ZeroCrossingDetectors.html

which references this:

http://www.ko4bb.com/~bruce/GeneralisedCollinsHardLimiterPaperV3B.pdf


Dont you work for Rakon? I bet their library can get a copy of
Collins.

Joe Gwinn

Kevin Aylward
Guest

Tue Jan 15, 2019 8:45 pm   



"Joseph Gwinn" wrote in message
news:0001HW.21ED838A06B4E96670000291B2CF_at_news.giganews.com...

On Jan 14, 2019, Kevin Aylward wrote
(in article<FMadnTn488qibKHBnZ2dnUU7-cPNnZ2d_at_giganews.com>):

Quote:
"Gerhard Hoffmann" wrote in message
news:g9caliF73srU1_at_mid.individual.net...


But if you controlled the sustaining current more carefully you
wouldn't
need a limiter.

This is not the limiting of the oscillator, it is the squaring up
*comparator* that converts the sine wave to rectangle. Its mandatory.
to
have a square wave output. The oscillator amplitude limiting to have
the
gain equal to one is a different issue.

That is not exactly big news.

Oliver Collins: The design of low jitter hard limiters
https://ieeexplore.ieee.org/document/494304

(I have seen it outside of the IEEE Wall Of Shame in the wilderness
of the internet.)

I have not located a copy yet. However, I have found references that
discuss it.

http://www.ko4bb.com/~bruce/ZeroCrossingDetectors.html

which references this:

http://www.ko4bb.com/~bruce/GeneralisedCollinsHardLimiterPaperV3B.pdf

Dont you work for Rakon? I bet their library can get a copy of


Fortunately, someone has now sent me a copy.

I had fair read of it. The theory just does not apply to precision
oscillator limiters. Some of the assumptions that are not met, are actually
stated in the paper.

A key point is that this analysis is geared to squaring up say, a 100 Hz
signal, which needs very large gain to get the slop up to 10 ns precision
(jitter), let alone the < 100 fs I am dealing with. That is, say a 500 mV to
1V sine at 25 MHz, squaring it up to 25 MHz square, at 100fs jitter. The
amplifiers are highly non-linear, so pretty much kills the whole analyses in
the paper. 1/f up-conversion is a major issue, again the paper is unable to
deal with that, let alone the noise of the limiter modulating the
capacitance seen at the oscillator tank causing additional phase noise. That
is, the limiter is part of the oscillator loop. You have to design with the
oscillator connected to the limiter in a oner to get accurate results.

The only practically way to design competitive low phase noise limiters
today, is to use commercial, very expensive, phase noise analysis software.
I reference on my site papers that show how stunningly difficult it is to
calculate phase noise:

http://www.kevinaylward.co.uk/ee/phasenoise/A-Demir.pdf

Hand calculations simply don't work. The equations for Phase Noise are just
too intractable.

-- Kevin Aylward
http://www.anasoft.co.uk - SuperSpice
http://www.kevinaylward.co.uk/ee/index.html

Joseph Gwinn
Guest

Thu Jan 17, 2019 4:45 am   



On Jan 15, 2019, Kevin Aylward wrote
(in article<7b-dnZplyvoHqqPBnZ2dnUU7-UvNnZ2d_at_giganews.com>):

Quote:
"Joseph Gwinn" wrote in message
news:0001HW.21ED838A06B4E96670000291B2CF_at_news.giganews.com...

On Jan 14, 2019, Kevin Aylward wrote
(in article<FMadnTn488qibKHBnZ2dnUU7-cPNnZ2d_at_giganews.com>):

"Gerhard Hoffmann" wrote in message
news:g9caliF73srU1_at_mid.individual.net...


But if you controlled the sustaining current more carefully you
wouldn't
need a limiter.

This is not the limiting of the oscillator, it is the squaring up
*comparator* that converts the sine wave to rectangle. Its mandatory.
to
have a square wave output. The oscillator amplitude limiting to have
the
gain equal to one is a different issue.

That is not exactly big news.

Oliver Collins: The design of low jitter hard limiters
https://ieeexplore.ieee.org/document/494304

(I have seen it outside of the IEEE Wall Of Shame in the wilderness
of the internet.)

I have not located a copy yet. However, I have found references that
discuss it.

http://www.ko4bb.com/~bruce/ZeroCrossingDetectors.html

which references this:

http://www.ko4bb.com/~bruce/GeneralisedCollinsHardLimiterPaperV3B.pdf

Dont you work for Rakon? I bet their library can get a copy of

Fortunately, someone has now sent me a copy.

I had fair read of it. The theory just does not apply to precision
oscillator limiters. Some of the assumptions that are not met, are actually
stated in the paper.

A key point is that this analysis is geared to squaring up say, a 100 Hz
signal, which needs very large gain to get the slop up to 10 ns precision
(jitter), let alone the < 100 fs I am dealing with. That is, say a 500 mV to
1V sine at 25 MHz, squaring it up to 25 MHz square, at 100fs jitter. The
amplifiers are highly non-linear, so pretty much kills the whole analyses in
the paper. 1/f up-conversion is a major issue, again the paper is unable to
deal with that, let alone the noise of the limiter modulating the
capacitance seen at the oscillator tank causing additional phase noise. That
is, the limiter is part of the oscillator loop. You have to design with the
oscillator connected to the limiter in a oner to get accurate results.


Yes. Collins was addressing the design of the zero crossing detector function
of a DMTD (Dual Mixer Time Difference) test set. The beatnote to be squared
up is often 1 Hz. Its pretty well impossible to shield such a low
frequency, but thats another story.

..<https://tf.nist.gov/phase/Properties/one.htm>

But the analytical approach is not limited to that scenario. Collins math
does not require any specific end-to-end gain.

Quote:
The only practically way to design competitive low phase noise limiters
today, is to use commercial, very expensive, phase noise analysis software.


Like what? If money were no object, which is best?

Quote:
I reference on my site papers that show how stunningly difficult it is to
calculate phase noise:

http://www.kevinaylward.co.uk/ee/phasenoise/A-Demir.pdf

Hand calculations simply don't work. The equations for Phase Noise are just
too intractable.
I dont doubt it. Ill read A-Demir.


Joe Gwinn

Kevin Aylward
Guest

Fri Jan 18, 2019 3:45 pm   



Quote:
"Joseph Gwinn" wrote in message
news:0001HW.21F02C6C0754805170000291B2CF_at_news.giganews.com...


Quote:

I had fair read of it. The theory just does not apply to precision
oscillator limiters. Some of the assumptions that are not met, are
actually
stated in the paper.

A key point is that this analysis is geared to squaring up say, a 100 Hz
signal, which needs very large gain to get the slop up to 10 ns precision
(jitter), let alone the < 100 fs I am dealing with. That is, say a 500
mV to
1V sine at 25 MHz, squaring it up to 25 MHz square, at 100fs jitter. The
amplifiers are highly non-linear, so pretty much kills the whole analyses
in
the paper. 1/f up-conversion is a major issue, again the paper is unable
to
deal with that, let alone the noise of the limiter modulating the
capacitance seen at the oscillator tank causing additional phase noise.
That
is, the limiter is part of the oscillator loop. You have to design with
the
oscillator connected to the limiter in a oner to get accurate results.

Yes. Collins was addressing the design of the zero crossing detector
function
of a DMTD (Dual Mixer Time Difference) test set. The beatnote to be squared
up is often 1 Hz. Its pretty well impossible to shield such a low
frequency, but thats another story.


Quote:
But the analytical approach is not limited to that scenario. Collins math
does not require any specific end-to-end gain.


The assumptions/axioms of the paper are simply not true for the design of
limiters squaring up oscillators. Such limiters are highly nonlinear in gain
and *phase*.

As I noted, and you noted, the paper to get to grips as to why, for example,
assuming linear amplifiers, with linear capacitors will get you errors of
like 50 dB.

http://www.kevinaylward.co.uk/ee/phasenoise/A-Demir.pdf

I have it more tractable explained on my site. Demir didn't actually
explain, physically, in his example in the paper, why it gave 50 dB errors
from the H-L approach. The reason, is that he had varactors directly across
the transistors. This mean 1/f noise modulated the varactors directly. In a
er.. competent design, one never connects the varactors like this. One uses
a blocking cap, say 10s pF which stops the 1/f noise getting to the cap.
The H-L method simply falls all over (as does the Collins paper) when there
are nonlinear time constants, as indeed there are in ALL real circuits.

http://www.kevinaylward.co.uk/ee/phasenoise/phasenoise.html

Quote:
The only practically way to design competitive low phase noise limiters
today, is to use commercial, very expensive, phase noise analysis
software.

Like what? If money were no object, which is best?


There are pretty much only 3 options

1 Agilent ADS
2 Cadence RF
3 Mentor Graphics RF

You are talking $100k per seat per year.

Mentor Graphics bought Berkeley Design Systems, who implemented the
technique in the A-Demir paper above. It's the best.

A key bit in Cadence RF, for example, is that it prints out an ordered list
of the noise contributors. This allows a systematic trial and error homing
in on the optimum combination of device sizes, current, noise over frequency
etc.

There are various trade-offs. e.g 1/f noise goes with sqrt(W.L) (MOS),
however, so the capacitance goes with WL, which is nonlinear, which reflects
to the oscillator...

Typically, one runs 1000s of sims to get the best compromise specs

There are no free PSS/PNOISE as far as I know, although when I last checked
for ngspice, they were making attempts to incorporate PSS (periodic steady
state).

I usually use the Shooting Method option, not Harmonic Balance. It's,
arguably better for non-linear circuits.

Kevin Aylward
kevin_at_kevinaylward.co.uk
www.kevinaylward.co.uk

Gerhard Hoffmann
Guest

Fri Jan 18, 2019 6:45 pm   



Am 18.01.19 um 15:42 schrieb Kevin Aylward:

Quote:
1 Agilent ADS
2 Cadence RF
3 Mentor Graphics RF

You are talking $100k per seat per year.


And Ansoft Microwave Harmonica, maybe Genesys.


Quote:
There are no free PSS/PNOISE as far as I know, although when I last
checked for ngspice, they were making attempts to incorporate PSS
(periodic steady state).


There is QUCS / QUCS Studio that can do harmonic balance at least.

< http://dd6um.darc.de/QucsStudio/qucsstudio.html >
< http://dd6um.darc.de/QucsStudio/screenshots.html >

Third party tutorials:
< http://www.gunthard-kraus.de/ >
< http://www.gunthard-kraus.de/qucsstudio/Tutorial_part%202_HB.pdf >

Qucs Studio is the version maintained by the original author. There
is also qucs without -studio which seems more outdated, maintained by
the rest of the developer group after a divorce.

It is open source and belongs loosely to the kicad universe.
Installation is simple: there is none. Unzip to a directory of your
choice and execute the main program.


regards,
Gerhard

Joseph Gwinn
Guest

Sat Jan 19, 2019 12:45 am   



On Jan 18, 2019, Kevin Aylward wrote
(in article<x4OdnVqW5rdweNzBnZ2dnUU7-afNnZ2d_at_giganews.com>):

Quote:
"Joseph Gwinn" wrote in message
news:0001HW.21F02C6C0754805170000291B2CF_at_news.giganews.com...


I had fair read of it. The theory just does not apply to precision
oscillator limiters. Some of the assumptions that are not met, are
actually
stated in the paper.

A key point is that this analysis is geared to squaring up say, a 100 Hz
signal, which needs very large gain to get the slop up to 10 ns precision
(jitter), let alone the < 100 fs I am dealing with. That is, say a 500
mV to
1V sine at 25 MHz, squaring it up to 25 MHz square, at 100fs jitter. The
amplifiers are highly non-linear, so pretty much kills the whole analyses
in
the paper. 1/f up-conversion is a major issue, again the paper is unable
to
deal with that, let alone the noise of the limiter modulating the
capacitance seen at the oscillator tank causing additional phase noise.
That
is, the limiter is part of the oscillator loop. You have to design with
the
oscillator connected to the limiter in a oner to get accurate results.

Yes. Collins was addressing the design of the zero crossing detector
function
of a DMTD (Dual Mixer Time Difference) test set. The beatnote to be squared
up is often 1 Hz. Its pretty well impossible to shield such a low
frequency, but thats another story.

But the analytical approach is not limited to that scenario. Collins math
does not require any specific end-to-end gain.

The assumptions/axioms of the paper are simply not true for the design of
limiters squaring up oscillators. Such limiters are highly nonlinear in gain
and *phase*.

As I noted, and you noted, the paper to get to grips as to why, for example,
assuming linear amplifiers, with linear capacitors will get you errors of
like 50 dB.


Something is circular here: Modeling a varactor as a linear capacitor isnt
going to work, unless small-signal approximations are good enough.

[snipped text - Ill re-read phase noise.html]

Quote:

The only practical way to design competitive low phase noise limiters
today, is to use commercial, very expensive, phase noise analysis
software.

Like what? If money were no object, which is best?

There are pretty much only 3 options

1 Agilent ADS
2 Cadence RF
3 Mentor Graphics RF

You are talking $100k per seat per year.


I know people with access to these.

I bet that Demir also has access to these tools at Bell Labs, and the reason
why he didnt address why the 50 dB problem was that he had not been able
to figure it out. He might appreciate an email pointing a possible cause out.

Quote:

Mentor Graphics bought Berkeley Design Systems, who implemented the
technique in the A-Demir paper above. It's the best.

A key bit in Cadence RF, for example, is that it prints out an ordered list
of the noise contributors. This allows a systematic trial and error homing
in on the optimum combination of device sizes, current, noise over frequency
etc.

There are various trade-offs. e.g 1/f noise goes with sqrt(W.L) (MOS),
however, so the capacitance goes with WL, which is nonlinear, which reflects
to the oscillator...

Typically, one runs 1000s of sims to get the best compromise specs.

There are no free PSS/PNOISE as far as I know, although when I last checked
for ngspice, they were making attempts to incorporate PSS (periodic steady
state).

I usually use the Shooting Method option, not Harmonic Balance. It's,
arguably better for non-linear circuits.


By Shooting Method I assume that you mean a standard way to solve
differential equations. Certainly often the only way for nonlinear diffeqs,
such as those arising in Demirs approach.

Joe Gwinn

Quote:

Kevin Aylward
kevin_at_kevinaylward.co.uk
www.kevinaylward.co.uk


Kevin Aylward
Guest

Sun Jan 20, 2019 12:45 am   



Quote:
"Joseph Gwinn" wrote in message
news:0001HW.21F295BB07E530AE70000291B2CF_at_news.giganews.com...


Quote:
Yes. Collins was addressing the design of the zero crossing detector
function
of a DMTD (Dual Mixer Time Difference) test set. The beatnote to be
squared
up is often 1 Hz. It´s pretty well impossible to shield such a low
frequency, but that´s another story.

But the analytical approach is not limited to that scenario. Collins´
math
does not require any specific end-to-end gain.

The assumptions/axioms of the paper are simply not true for the design of
limiters squaring up oscillators. Such limiters are highly nonlinear in
gain
and *phase*.

As I noted, and you noted, the paper to get to grips as to why, for
example,
assuming linear amplifiers, with linear capacitors will get you errors of
like 50 dB.

Something is circular here: Modeling a varactor as a linear capacitor isn´t
going to work, unless small-signal approximations are good enough.


I don't understand your point.

The Hajimiri-Lee approach assumes linear components, but time varying. So,
sure, that doesn't work.

This shows why, without the maths :-)

http://www.kevinaylward.co.uk/ee/phasenoise/OrthogonalPerturbation.xht

The Collins paper assumes that only noise near the x-ing point matters. This
is not true with non-linear capacitance (or time constants), with the
waveform being significantly dependant on that capacitance. If the
capacitance changes due to noise, far away from the switching point, it
changes the time that it takes for the signal to reach the next x-ing point.
This means that all noise everywhere generates jitter/phase noise.

This is so trivially obvious, that it is somewhat stunning that the H-L
approach got/has so much credibility.


Quote:

The only practical way to design competitive low phase noise limiters
today, is to use commercial, very expensive, phase noise analysis
software.

Like what? If money were no object, which is best?

There are pretty much only 3 options

1 Agilent ADS
2 Cadence RF
3 Mentor Graphics RF

You are talking $100k per seat per year.

I know people with access to these.


Well, I do, as does any IC designer.

Quote:
I bet that Demir also has access to these tools at Bell Labs, and the
reason
why he didn´t address why the 50 dB problem was that he had not been able
to figure it out. He might appreciate an email pointing a possible cause
out.


Again, you are confusing me here. Demir's approach *is* the method that
shows that H-L is off by 50dB. That's was what Dimir was specifically
addressing.

The Dimir paper just didn't explain *physically* why/how, i.e. in a way us
engineers could understand. It was all maths. “orthogonal perturbation to
the tangent of the limit cycle” isn't actually intuitive as to what it
means.

Quote:

Mentor Graphics bought Berkeley Design Systems, who implemented the
technique in the A-Demir paper above. It's the best.

A key bit in Cadence RF, for example, is that it prints out an ordered
list
of the noise contributors. This allows a systematic trial and error homing
in on the optimum combination of device sizes, current, noise over
frequency
etc.

There are various trade-offs. e.g 1/f noise goes with sqrt(W.L) (MOS),
however, so the capacitance goes with WL, which is nonlinear, which
reflects
to the oscillator...

Typically, one runs 1000s of sims to get the best compromise specs.

There are no free PSS/PNOISE as far as I know, although when I last
checked
for ngspice, they were making attempts to incorporate PSS (periodic
steady
state).

I usually use the Shooting Method option, not Harmonic Balance. It's,
arguably better for non-linear circuits.

By Shooting Method I assume that you mean a standard way to solve
differential equations. Certainly often the only way for nonlinear diffeqs,
such as those arising in Demir´s approach.


Yes.

https://en.wikipedia.org/wiki/Shooting_method

The shooting method is another way to get the steady state time domain
response. It solves in the time domain, where as harmonic balance does this
in the frequency domain. It gives a "cleaner" waveform. No harmonic ripples
on square waves.

Phase noise calculations doesn't care how the steady state waveform is
calculated . It just uses that result to compute the effect of noise at
every point in the waveform to drive it own number cruncher.


-- Kevin Aylward
http://www.anasoft.co.uk - SuperSpice
http://www.kevinaylward.co.uk/ee/index.html

Gerhard Hoffmann
Guest

Sun Jan 20, 2019 3:45 am   



Am 20.01.19 um 00:00 schrieb Kevin Aylward:
Quote:
"Joseph Gwinn"  wrote in message
news:0001HW.21F295BB07E530AE70000291B2CF_at_news.giganews.com...


Yes. Collins was addressing the design of the zero crossing detector
function
of a DMTD (Dual Mixer Time Difference) test set. The beatnote to be
squared
up is often 1 Hz. It´s pretty well impossible to shield such a low
frequency, but that´s another story.


I have made such a DMTD system to compare a "Space Hydrogen Maser"
to a to a Cesium, also in space. Being at micro gravity makes it
easier to concentrate on / interrogate only a small number of atoms.
Easier than a fountain, good for precision.

Low frequency shielding is not much of a problem. Keeping the coupling
areas small is a key, and there is a lot of milled metal around to
get rid of the heat.

The low frequency stages are handled in the digital domain anyway
in a corner of a largish Virtex.


Quote:
The Collins paper assumes that only noise near the x-ing point matters.
This is not true with non-linear capacitance (or time constants), with
the waveform being significantly dependant on that capacitance. If the
capacitance changes due to noise, far away from the switching point, it
changes the time that it takes for the signal to reach the next x-ing
point. This means that all noise everywhere generates jitter/phase noise.

This is so trivially obvious, that it is somewhat stunning that the H-L
approach got/has so much credibility.


All the world is not a VAX, and all oscillators are not on a tiny chip.
Collins style filtering /slope gain requires serious, time/input
invariant filters, and you do not have them on your chips. There is no
way to get the 100 MHz signal properly filtered and also the 1 Hz
version without resorting to external resources. A 30 pF Sio2
compensation capacitor was already a royal pain back in 741 times; the
situation has not significantly improved. Onchip you have just small
caps that vary with everything else: temp, supplies, bias, amplitude.
There are no inductors that allow easy gain at RF and no gain at 1/f.
No gain in the /f region is a good thing because there is nothing to be
up converted to begin with.

There are no oscillator chips in a BVA oscillator.

The real problem with HL is that it does not give a recipe for design.
In the best case you can see why your design failed.


Quote:


There are various trade-offs. e.g 1/f noise goes with sqrt(W.L) (MOS),
however, so the capacitance goes with WL, which is nonlinear, which
reflects
to the oscillator...

Typically, one runs 1000s of sims to get the best compromise specs.


That does not sound like engineering, it looks more like staggering
blindly through the solution space and keeping the best one happens to find.

regards,
Gerhard


Guest

Sun Jan 20, 2019 5:45 am   



On Sunday, January 20, 2019 at 1:31:32 PM UTC+11, Gerhard Hoffmann wrote:
Quote:
Am 20.01.19 um 00:00 schrieb Kevin Aylward:
"Joseph Gwinn"  wrote in message


<snip>

Quote:
Typically, one runs 1000s of sims to get the best compromise specs.

That does not sound like engineering, it looks more like staggering
blindly through the solution space and keeping the best one happens to find.


That the first time I've seen Kevin Aylward put in the same category as John Larkin. That would be ruder to Kevin than it is to John, if Kevin weren't working in a much more restricted design space.

--
Bill Sloman, Sydney

Kevin Aylward
Guest

Sun Jan 20, 2019 2:45 pm   



-----Original Message-----
Quote:
From: Gerhard Hoffmann
There are various trade-offs. e.g 1/f noise goes with sqrt(W.L) (MOS),
however, so the capacitance goes with WL, which is nonlinear, which
reflects
to the oscillator...

Typically, one runs 1000s of sims to get the best compromise specs.

That does not sound like engineering, it looks more like staggering
blindly through the solution space and keeping the best one happens to
find.


Ahmmmm.......

Simply not true. Maybe for AI that's an adequate description.

Sure, one can do it "blindly", but that isn't what is done.

I have explained this many times before. That view shows a lack of
understanding how modern designs with billions of transistors is actually
done today. Running 100,000s of simulations is the only way to produce a
reliable product, that is competitive in the market place. Its what
everyone designing ASICS does. Period. End of story.

For starters, even a single transistor amplifier is closed form analytically
intractable. Even the idealised one transistor Widlar source gets you into
transcendental functions. Adding in early effect, base spreading resistance,
and your nacked.

http://www.kevinaylward.co.uk/ee/widlarlambert/widlarlambert.xht

Its is why spice was invented. To solve vast arrays of non-linear systems of
equations impossible to solve in the mind, Steven Hawking not withstanding.

For example, an optimised LDO circuit with 50 transistors has no chance of
being reliably designed on paper, today. That's just a fact.

Lets look just at stability. Small signal analysis isn't enough. The loop
phase/gain changes all over a transient pulse waveform, such that small
signal analysis often fails to show real instability. Transient is the only
way to ensure a reliable design. "Sound engineering" is designing for worst
case over all process variations, and operating conditions. Simply
impossible without running large numbers of simulations. e.g.

http://www.anasoft.co.uk/images/worst_case.png

So, for example, an LDO, needs to satisfy noise, stability, regulation...
over all processes condition and temperature,

Just considering Max/Min extremes. Its max/min RC, max/min npn, max/min
pnp, max/min nmos, max/min pmos, max/min vsupply, max/min temp, max/min
rload, max/min cload. That's 256 combinations for starters.

Now, say there are two comp caps and two comp resisters. To locate the
optimum value for those components, over all those operating conditions.
Lets say the initial sweep of values is say, from 10 ohms to 100k, and 1 pf
to 100pf, at 5p and 100 ohm steps, its 10,000s of runs. Then after homing in
on the optimum solutions, runs at finer steps are made.

It is standard to get one off corners that are unstable, and moving the
component a small amount makes another corner unstable. It is usually a fine
balancing act. Sure, if one wanted 1Hz BW, and 20 dB PSRR, sure stick a 1nf
cap on a node. Now try and sell the part with that performance.

Anyone that actually does ASIC design is going to be ROTFLAMO on the idea
that this is some sort of idiots way of designing. It is mandatory in any
mainstream commercial companies. Its part of the sign off process. There is
no other way of doing it.

Of course, to design the LDO, you need to understand topologies,
qualitivity, like how number of stages, device sizes (W/L), voltage ratings,
etc effect the performance specifications being targeted. You can't start
from a blank slate.

You appear to be confusing a designer that technically knows the one or two
places to connect a compensation capacitor, how noise varies with current,
how BW varies with current and capacitance, or when to use a folded cascode,
or an emitter follower with a monkey at a typewriter.

The method we all use, is the Darwinian algorithm of replication, random
variation, and selection, because, embarrassing or not, that is how the
brain actually works. Thi algorithm is not the same one the monkey uses,
despite creationists believing it is.

Kevin Aylward
http://www.anasoft.co.uk - SuperSpice
http://www.kevinaylward.co.uk/ee/index.html

Tim Williams
Guest

Sun Jan 20, 2019 11:45 pm   



"Kevin Aylward" <kevinRemovAT_at_kevinaylward.co.uk> wrote in message
news:ZYmdnbksEo-x7dnBnZ2dnUU78W_NnZ2d_at_giganews.com...
Quote:
Running 100,000s of simulations is the only way to produce a reliable
product, that is competitive in the market place. Its what everyone
designing ASICS does. Period. End of story.


To put it another way:

"Correlation does not imply causation", but it strongly hints at it. And
enough correlations (and non-correlations) between all known parameters of
the system, together, can prove causality between the few variables that are
of interest.

Most crap science you see reported in the news is just finding correlations,
with a few important and well-designed studies going the trouble to actually
prove their point (where "proof" is a measure of statistical confidence, as
it is in all experimental sciences).

Tim

--
Seven Transistor Labs, LLC
Electrical Engineering Consultation and Design
Website: https://www.seventransistorlabs.com/

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