Help with PSPICE digital simulation

hello everyone,

i'm trying to simulate flip-flop circuits using nand gates only
(cross-coupled nand gates) for a school project with PSPICE. however
the outputs of my nand gates ( Q and Qnot ) always seem to be at the
"don't care" (or "X") state after i run the simulation. is this
because the simulator doesn't know what are the initial states of Q
and Qnot. is there a way around this? any help is appreciated. thank
you.

patrick antoun

On 12 Mar 2005 16:46:16 -0800, patrickantoun_at_hotmail.com (Patrick)
wrote:

hello everyone,

i'm trying to simulate flip-flop circuits using nand gates only
(cross-coupled nand gates) for a school project with PSPICE. however
the outputs of my nand gates ( Q and Qnot ) always seem to be at the
"don't care" (or "X") state after i run the simulation. is this
because the simulator doesn't know what are the initial states of Q
and Qnot. is there a way around this? any help is appreciated. thank
you.

patrick antoun

Digital Setup, Flip-Flop Initialization

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice:(480)460-2350 | |
| E-mail Address at Website Fax:(480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

On 12 Mar 2005 16:46:16 -0800, patrickantoun_at_hotmail.com (Patrick)
wrote:

hello everyone,

i'm trying to simulate flip-flop circuits using nand gates only
(cross-coupled nand gates) for a school project with PSPICE. however
the outputs of my nand gates ( Q and Qnot ) always seem to be at the
"don't care" (or "X") state after i run the simulation. is this
because the simulator doesn't know what are the initial states of Q
and Qnot. is there a way around this? any help is appreciated. thank
you.

patrick antoun

Digital Setup, Flip-Flop Initialization

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice:(480)460-2350 | |
| E-mail Address at Website Fax:(480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.

thanks, will this work (digital setup) even though i'm not actually
using any flip-flops (my circuit has only cross-coupled nand gates)?
If so, where do i find this digital setup?
patrick


[snip]

Jim Thompson wrote:
On 13 Mar 2005 09:16:05 -0800, patrickantoun_at_hotmail.com (Patrick)
wrote:


thanks, will this work (digital setup) even though i'm not actually
using any flip-flops (my circuit has only cross-coupled nand gates)?
If so, where do i find this digital setup?
patrick



[snip]

Analysis Setup

You could also try a .IC=0 (initial condition) on one of the NAND
outputs.

...Jim Thompson
Patrick,
Take a look at your design. What is setting the state at start-up?
Your design SHOULD include signal or circuitry to set that initial state
at the beginning. Even if you have a few digital sources that go from 0
or 1 to Z (high impedance) just to kick things off...

--
Charlie

On 13 Mar 2005 09:16:05 -0800, patrickantoun_at_hotmail.com (Patrick)
wrote:


thanks, will this work (digital setup) even though i'm not actually
using any flip-flops (my circuit has only cross-coupled nand gates)?
If so, where do i find this digital setup?
patrick



[snip]

Analysis Setup

You could also try a .IC=0 (initial condition) on one of the NAND
outputs.

...Jim Thompson
Patrick,

On Mon, 14 Mar 2005 10:14:49 -0800, Charles Edmondson
edmondson_at_ieee.org> wrote:


Jim Thompson wrote:

On 13 Mar 2005 09:16:05 -0800, patrickantoun_at_hotmail.com (Patrick)
wrote:



thanks, will this work (digital setup) even though i'm not actually
using any flip-flops (my circuit has only cross-coupled nand gates)?
If so, where do i find this digital setup?
patrick



[snip]

Analysis Setup

You could also try a .IC=0 (initial condition) on one of the NAND
outputs.

...Jim Thompson

Patrick,
Take a look at your design. What is setting the state at start-up?
Your design SHOULD include signal or circuitry to set that initial state
at the beginning. Even if you have a few digital sources that go from 0
or 1 to Z (high impedance) just to kick things off...

--
Charlie


Hmmmm?

Charlie,

Am I learning a NEW trick? Can part "DigStim" do that, 0 -> Z? Or
what part should I use?

...Jim Thompson
Wellll.... you could, but that invokes the stimulus editor.

Jim Thompson wrote:
On Mon, 14 Mar 2005 10:14:49 -0800, Charles Edmondson
edmondson_at_ieee.org> wrote:


Jim Thompson wrote:

On 13 Mar 2005 09:16:05 -0800, patrickantoun_at_hotmail.com (Patrick)
wrote:



thanks, will this work (digital setup) even though i'm not actually
using any flip-flops (my circuit has only cross-coupled nand gates)?
If so, where do i find this digital setup?
patrick



[snip]

Analysis Setup

You could also try a .IC=0 (initial condition) on one of the NAND
outputs.

...Jim Thompson

Patrick,
Take a look at your design. What is setting the state at start-up?
Your design SHOULD include signal or circuitry to set that initial state
at the beginning. Even if you have a few digital sources that go from 0
or 1 to Z (high impedance) just to kick things off...

--
Charlie


Hmmmm?

Charlie,

Am I learning a NEW trick? Can part "DigStim" do that, 0 -> Z? Or
what part should I use?

...Jim Thompson
Wellll.... you could, but that invokes the stimulus editor.

I would use a stim1 part. That lets you give it a series of commands in
time state format.
0s 0
1us 1
2us Z

is one such command sequence. The other stim parts let you have buss
stimulus defined.

--
Charlie

Patrick,
Take a look at your design. What is setting the state at start-up?
Your design SHOULD include signal or circuitry to set that initial state
at the beginning. Even if you have a few digital sources that go from 0
or 1 to Z (high impedance) just to kick things off...

--
Charlie

Patrick,
Take a look at your design. What is setting the state at start-up?
Your design SHOULD include signal or circuitry to set that initial state
at the beginning. Even if you have a few digital sources that go from 0
or 1 to Z (high impedance) just to kick things off...

--
Charlie

Charlie,
Since i'm new to digital simulation using PSPICE 9.2.X i guess i don't
have anything that sets the state of the outputs (Q and Qnot) of the
cross-coupled nand gates. if i was actually writing the netlist i
would include a .IC or .NODESET command. but since Capture is all GUI
i don't know how to include this kind of initial condition in my
circuit.
i tried connecting a 10k pull-up resistor for the output of one nand
gate (Q) to VCC. this seemed to sort of work, but it makes the circuit
analog/digital (by introducing analog components) and the square wave
at the output of the flip-flop wasn't as nice looking and the clock
source. there must be a way to accomplish this without having to use a
pull-up resistor.
ultimately i'm trying to simulate a clocked JK flip-flop (with preset
and reset asynchronous inputs) using 2-input and 3-input nand gates.
this is for a school project. i greatly appreciate and help with this
problem. thanks again.

Patrick

On Mon, 14 Mar 2005 16:59:54 -0800, Charles Edmondson
edmondson_at_ieee.org> wrote:


Jim Thompson wrote:

On Mon, 14 Mar 2005 10:14:49 -0800, Charles Edmondson
edmondson_at_ieee.org> wrote:



Jim Thompson wrote:


On 13 Mar 2005 09:16:05 -0800, patrickantoun_at_hotmail.com (Patrick)
wrote:




thanks, will this work (digital setup) even though i'm not actually
using any flip-flops (my circuit has only cross-coupled nand gates)?
If so, where do i find this digital setup?
patrick



[snip]

Analysis Setup

You could also try a .IC=0 (initial condition) on one of the NAND
outputs.

...Jim Thompson

Patrick,
Take a look at your design. What is setting the state at start-up?
Your design SHOULD include signal or circuitry to set that initial state
at the beginning. Even if you have a few digital sources that go from 0
or 1 to Z (high impedance) just to kick things off...

--
Charlie


Hmmmm?

Charlie,

Am I learning a NEW trick? Can part "DigStim" do that, 0 -> Z? Or
what part should I use?

...Jim Thompson

Wellll.... you could, but that invokes the stimulus editor.

I would use a stim1 part. That lets you give it a series of commands in
time state format.
0s 0
1us 1
2us Z

is one such command sequence. The other stim parts let you have buss
stimulus defined.

--
Charlie


I called it by the wrong name. That will be VERY useful... THANKS!

...Jim Thompson
No Problem!

On 14 Mar 2005 19:40:07 -0800, patrickantoun_at_hotmail.com (Patrick)
wrote:


Patrick,
Take a look at your design. What is setting the state at start-up?
Your design SHOULD include signal or circuitry to set that initial state
at the beginning. Even if you have a few digital sources that go from 0
or 1 to Z (high impedance) just to kick things off...

--
Charlie

Charlie,
Since i'm new to digital simulation using PSPICE 9.2.X i guess i don't
have anything that sets the state of the outputs (Q and Qnot) of the
cross-coupled nand gates. if i was actually writing the netlist i
would include a .IC or .NODESET command. but since Capture is all GUI
i don't know how to include this kind of initial condition in my
circuit.
i tried connecting a 10k pull-up resistor for the output of one nand
gate (Q) to VCC. this seemed to sort of work, but it makes the circuit
analog/digital (by introducing analog components) and the square wave
at the output of the flip-flop wasn't as nice looking and the clock
source. there must be a way to accomplish this without having to use a
pull-up resistor.
ultimately i'm trying to simulate a clocked JK flip-flop (with preset
and reset asynchronous inputs) using 2-input and 3-input nand gates.
this is for a school project. i greatly appreciate and help with this
problem. thanks again.

Patrick


Charlie told us how...

"I would use a stim1 part. That lets you give it a series of commands
in time state format"

(Use part named "STIM1")

0s 0
1us Z

Tie to one Q of the cross-coupled NANDs.

...Jim Thompson
And, depending on your set up, you might need the complement on the

Jim Thompson wrote:
[snip]

I called it by the wrong name. That will be VERY useful... THANKS!

...Jim Thompson
No Problem!

Just remember that this uses the standard stim set up in digio.lib, so
it is typically 0-5v, and goes up to about 2Ghz reliably.

Also, the Z is what is set up in your digital options, so if you need a
really high Z (the default IIRC is only 10K) you need to change your
options.
--
Charlie

On Tue, 15 Mar 2005 09:59:36 -0800, Charles Edmondson
edmondson_at_ieee.org> wrote:


Jim Thompson wrote:

[snip]

I called it by the wrong name. That will be VERY useful... THANKS!

...Jim Thompson

No Problem!

Just remember that this uses the standard stim set up in digio.lib, so
it is typically 0-5v, and goes up to about 2Ghz reliably.

Also, the Z is what is set up in your digital options, so if you need a
really high Z (the default IIRC is only 10K) you need to change your
options.
--
Charlie


Hi Charlie,

Looks like the library is actually named "dig_io.lib" ;-)

I find "Z" is 1Meg in most logic families, but 200K in TTL.

I couldn't find "Z" defined in relationship to "STIM1"

Where is that set?

...Jim Thompson