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elektroda.net NewsGroups Forum Index - Verilog Language - **Help on non-blocking assignment**

Guest

Sun Aug 12, 2018 4:45 am

Hello,

When I implement an integrator, I notice that there are two kinds of writing.

One looks like this:

always @(posedge clk)

begin

if (rst)

begin

d1 <= 0;

d2 <= 0;

count <= 0;

end else

begin

// Integrator section

d2 <= d1 + d2;

d1 <= d_in + d1;

if (count == decimation_ratio - 1)

begin

count <= 16'b0;

d_tmp <= d2;

end else

count <= count + 16'd1;

end

end

The other is reverse the sequence of these two lines:

d1 <= d_in + d1;

d2 <= d1 + d2;

I think there should be one delay difference for the two coding lines.

The delay unit can be put in the forward path, or in the feedback path.

But I don't see there is such a difference in simulation and in FPGA

implementation.

What is your opinion on this?

Thanks,

Guest

Sun Aug 12, 2018 10:45 pm

On Saturday, 8/11/2018 11:43 PM, Robert Willy wrote:

Hello,

When I implement an integrator, I notice that there are two kinds of writing.

One looks like this:

always @(posedge clk)

begin

if (rst)

begin

d1 <= 0;

d2 <= 0;

count <= 0;

end else

begin

// Integrator section

d2 <= d1 + d2;

d1 <= d_in + d1;

if (count == decimation_ratio - 1)

begin

count <= 16'b0;

d_tmp <= d2;

end else

count <= count + 16'd1;

end

end

The other is reverse the sequence of these two lines:

d1 <= d_in + d1;

d2 <= d1 + d2;

I think there should be one delay difference for the two coding lines.

The delay unit can be put in the forward path, or in the feedback path.

But I don't see there is such a difference in simulation and in FPGA

implementation.

What is your opinion on this?

Thanks,

When I implement an integrator, I notice that there are two kinds of writing.

One looks like this:

always @(posedge clk)

begin

if (rst)

begin

d1 <= 0;

d2 <= 0;

count <= 0;

end else

begin

// Integrator section

d2 <= d1 + d2;

d1 <= d_in + d1;

if (count == decimation_ratio - 1)

begin

count <= 16'b0;

d_tmp <= d2;

end else

count <= count + 16'd1;

end

end

The other is reverse the sequence of these two lines:

d1 <= d_in + d1;

d2 <= d1 + d2;

I think there should be one delay difference for the two coding lines.

The delay unit can be put in the forward path, or in the feedback path.

But I don't see there is such a difference in simulation and in FPGA

implementation.

What is your opinion on this?

Thanks,

The point of non-blocking assignments is that the two statements

operate in parallel, each using the value of the right-hand side

from just before the clock edge, and applying that value just after

the clock edge. So reversing the order of the statements has no

effect on the outcome.

--

Gabor

Guest

Mon Aug 13, 2018 5:45 pm

On Monday, August 13, 2018 at 2:50:29 AM UTC+5:30, Gabor wrote:

On Saturday, 8/11/2018 11:43 PM, Robert Willy wrote:

Hello,

When I implement an integrator, I notice that there are two kinds of writing.

One looks like this:

always @(posedge clk)

begin

if (rst)

begin

d1 <= 0;

d2 <= 0;

count <= 0;

end else

begin

// Integrator section

d2 <= d1 + d2;

d1 <= d_in + d1;

if (count == decimation_ratio - 1)

begin

count <= 16'b0;

d_tmp <= d2;

end else

count <= count + 16'd1;

end

end

The other is reverse the sequence of these two lines:

d1 <= d_in + d1;

d2 <= d1 + d2;

I think there should be one delay difference for the two coding lines.

The delay unit can be put in the forward path, or in the feedback path.

But I don't see there is such a difference in simulation and in FPGA

implementation.

What is your opinion on this?

Thanks,

The point of non-blocking assignments is that the two statements

operate in parallel, each using the value of the right-hand side

from just before the clock edge, and applying that value just after

the clock edge. So reversing the order of the statements has no

effect on the outcome.

--

Gabor

Hello,

When I implement an integrator, I notice that there are two kinds of writing.

One looks like this:

always @(posedge clk)

begin

if (rst)

begin

d1 <= 0;

d2 <= 0;

count <= 0;

end else

begin

// Integrator section

d2 <= d1 + d2;

d1 <= d_in + d1;

if (count == decimation_ratio - 1)

begin

count <= 16'b0;

d_tmp <= d2;

end else

count <= count + 16'd1;

end

end

The other is reverse the sequence of these two lines:

d1 <= d_in + d1;

d2 <= d1 + d2;

I think there should be one delay difference for the two coding lines.

The delay unit can be put in the forward path, or in the feedback path.

But I don't see there is such a difference in simulation and in FPGA

implementation.

What is your opinion on this?

Thanks,

The point of non-blocking assignments is that the two statements

operate in parallel, each using the value of the right-hand side

from just before the clock edge, and applying that value just after

the clock edge. So reversing the order of the statements has no

effect on the outcome.

--

Gabor

Yes. In an non-blocking block of assignments, the order of statements doesn't make any difference. (Provided LHS are distinct).

elektroda.net NewsGroups Forum Index - Verilog Language - **Help on non-blocking assignment**