Help on Gate count for the gated clock logic

Wed Mar 09, 2005 9:16 am   

Greetings,

I have an RTL code with the clock gating logic in RTL. The frequency
of operation of the device ie., the system clock is 25MHz, and the
gated clock is operating at 32kHz.

My question here is, i want to get the gate count for the gated clock
logic. I am using synopsys DC 2004.06. Is there any method to get the
gate count for the logic which is running on Gated clock?

Your comments and suggestion is of great help.


Thanks,
Regards
Kumar

Tue Apr 05, 2005 3:10 am   

When you use DC Shell, you can generate "reports" at the end of the
synthesis. You can generate an area report with -hier option, I believe
it should give you plenty information about the number of cells you
used. Of course, you can bound your gate count by dividing the toal
area of your chip with the area of a NAND2 with 1x drive cell. That
should be an upper bound of your gate count estimation.

James