EDAboard.com | EDAboard.de | EDAboard.co.uk | WTWH Media

HDLC Clocking

Ask a question - edaboard.com

elektroda.net NewsGroups Forum Index - VHDL Language - HDLC Clocking


Guest

Sat Aug 17, 2019 4:45 pm   



Is there a standard for the clocking in HDLC? I have seen examples where data is transmitted on rising edge of TXCLK and sampled on falling edge ... as well as examples where data is transmitted on falling edge of TXCLK and sampled on rising edge.

I can't seem to find any mention in the HDLC standard.

Rick C
Guest

Sat Aug 17, 2019 4:45 pm   



On Saturday, August 17, 2019 at 11:01:46 AM UTC-4, digita...@gmail.com wrote:
Quote:
Is there a standard for the clocking in HDLC? I have seen examples where data is transmitted on rising edge of TXCLK and sampled on falling edge ... as well as examples where data is transmitted on falling edge of TXCLK and sampled on rising edge.

I can't seem to find any mention in the HDLC standard.


HDLC doesn't seem to specify the clock. I would expect the clock to be specified at a lower level protocol. HDLC can be used over async links where no clock is transmitted. So clearly no clock edge could be specified in that case.

--

Rick C.

- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209

Richard Damon
Guest

Sat Aug 17, 2019 4:45 pm   



On 8/17/19 11:01 AM, digitalguy33_at_gmail.com wrote:
Quote:
Is there a standard for the clocking in HDLC? I have seen examples where data is transmitted on rising edge of TXCLK and sampled on falling edge ... as well as examples where data is transmitted on falling edge of TXCLK and sampled on rising edge.

I can't seem to find any mention in the HDLC standard.


I think the issue is that is a detail at a different level than the HDLC
standard, dealing with the physical transport layer. HDLC doesn't even
imply that there IS a clock transferred between units to worry about
what edge to use, and in fact has pieces that make sure there is enough
data transitions to allow for clock recovery operation in the receiver.

elektroda.net NewsGroups Forum Index - VHDL Language - HDLC Clocking

Ask a question - edaboard.com

Arabic version Bulgarian version Catalan version Czech version Danish version German version Greek version English version Spanish version Finnish version French version Hindi version Croatian version Indonesian version Italian version Hebrew version Japanese version Korean version Lithuanian version Latvian version Dutch version Norwegian version Polish version Portuguese version Romanian version Russian version Slovak version Slovenian version Serbian version Swedish version Tagalog version Ukrainian version Vietnamese version Chinese version Turkish version
EDAboard.com map