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HDL simple survey - what do you actually use

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Lars Asplund
Guest

Tue Feb 27, 2018 12:03 am   



VHDL + VUnit (https://vunit.github.io/index.html)

Regards,
Lars

Lars Asplund
Guest

Tue Feb 27, 2018 12:05 am   



VHDL + VUnit (https://vunit.github.io/index.html)

Regards,
Lars

Espen Tallaksen
Guest

Tue Feb 27, 2018 5:02 pm   



VHDL for design.
VHDL + UVVM (Universal VHDL Verification Methodology, Open source) for verification
https://github.com/UVVM/UVVM_All

Using VHDL with a good testbench architecture and a good infrastructure library allows very efficient verification.
BTW: UVVM also comes with open source BFMs (Bus Functional Models) and VVCs (VHDL Verification Components) for interfaces like AIX4-lite, AXI4-stream, Avalon MM, UART, I2C, SPI.

Tobias Baumann
Guest

Fri Mar 09, 2018 5:45 pm   



Quote:

VHDL for RTL (primarily FPGAs but ASIC in the past). VHDL + OSVVM for testbenches.


Same here. Even when not using OSVVM, I use VHDL primarly for my
testbenches, sometimes with PSL when needed.

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