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rickman
Guest

Sat Jan 13, 2018 9:57 am   



john p wrote on 1/12/2018 10:09 PM:
Quote:
On Wednesday, January 10, 2018 at 6:17:32 AM UTC-8, john wrote:
I'm trying to decide on which to use for a project as the main default that may
include a number of freelance people.

can you say which of these you actually use (the most)
and have the best skills in

Verilog
systemVerilog
SystemC
VHDL
Other

And if possible what type of work you use it for in general
I dont need to know why you use a particular one - and to avoid
flame wars request you dont explain that.

I'm just trying to get a general feel for what people here use regularly.

TIA

--

john

=========================
http://johntech.co.uk
=========================

Verilog, Verilog, Verilog.

I've been consulting for over 24 years now and I now focus exclusively on Verilog for a variety of reasons.

I've seen the Verilog vs VHDL discussion many times, it boils down to either a religious or toothpaste debate - what were you raised with or what flavor do you prefer.

I've found I am *much* more productive in Verilog.

At this point, I don't take on jobs in VHDL.

My $0.02.


I met a guy in another forum who said not only he, but a number of people he
has shown to use Verilog at work are much more productive. I've heard that
there are various defaults in Verilog that are real gotchas unless you know
about them. But no one has been able to point me to a book that describes
these issues. Can you suggest a good Verilog book that covers these
details? It doesn't have to be a beginner's book as I am pretty experienced
in HDL and have even done some work in Verilog. I just want to get to the
point that I won't be making student mistakes in my designs. Well, at least
no more than I do in VHDL.

--

Rick C

Viewed the eclipse at Wintercrest Farms,
on the centerline of totality since 1998

Thomas Heller
Guest

Sat Jan 13, 2018 1:29 pm   



Am 10.01.2018 um 15:17 schrieb john:
Quote:

I'm trying to decide on which to use for a project as the main default that may
include a number of freelance people.

can you say which of these you actually use (the most)
and have the best skills in

Verilog
systemVerilog
SystemC
VHDL
Other


Is use MyHDL which gets translated into VHDL for synthesis.

Thomas

BobH
Guest

Sat Jan 13, 2018 6:08 pm   



On 01/13/2018 12:57 AM, rickman wrote:
Quote:
I met a guy in another forum who said not only he, but a number of
people he has shown to use Verilog at work are much more productive.
I've heard that there are various defaults in Verilog that are real
gotchas unless you know about them.  But no one has been able to point
me to a book that describes these issues.  Can you suggest a good
Verilog book that covers these details?  It doesn't have to be a
beginner's book as I am pretty experienced in HDL and have even done
some work in Verilog.  I just want to get to the point that I won't be
making student mistakes in my designs.  Well, at least no more than I do
in VHDL.


The best Verilog reference book that I have found is "Verilog HDL A
Guide to Digital Design and Synthesis" by Samir Palnitkar. It is good
enough that it lives in my book bag to get hauled to work every day (and
shows it now). This is not really a beginners book, and it is not
perfect, but it is the best that I have found. There are at least two
editions of this out and there may be more. The second edition is the
one that is most useful to me.

For syntax questions, Stuart Sutherland's "Verilog HDL Quick Reference
Guide" is excellent. This document can be downloaded from Mr
Sutherland's web site. I work in Verilog and C depending on the phase of
the project that I am in (FPGA or firmware). Swapping between Verilog
and C means that looking up the exact syntax is necessary, especially
around the transitions.

BobH

rickman
Guest

Sat Jan 13, 2018 11:28 pm   



BobH wrote on 1/13/2018 11:08 AM:
Quote:
On 01/13/2018 12:57 AM, rickman wrote:
I met a guy in another forum who said not only he, but a number of people
he has shown to use Verilog at work are much more productive. I've heard
that there are various defaults in Verilog that are real gotchas unless
you know about them. But no one has been able to point me to a book that
describes these issues. Can you suggest a good Verilog book that covers
these details? It doesn't have to be a beginner's book as I am pretty
experienced in HDL and have even done some work in Verilog. I just want
to get to the point that I won't be making student mistakes in my
designs. Well, at least no more than I do in VHDL.


The best Verilog reference book that I have found is "Verilog HDL A Guide to
Digital Design and Synthesis" by Samir Palnitkar. It is good enough that it
lives in my book bag to get hauled to work every day (and shows it now).
This is not really a beginners book, and it is not perfect, but it is the
best that I have found. There are at least two editions of this out and
there may be more. The second edition is the one that is most useful to me.

For syntax questions, Stuart Sutherland's "Verilog HDL Quick Reference
Guide" is excellent. This document can be downloaded from Mr Sutherland's
web site. I work in Verilog and C depending on the phase of the project that
I am in (FPGA or firmware). Swapping between Verilog and C means that
looking up the exact syntax is necessary, especially around the transitions.


Do either of these books cover the defaults issue I mention above? I have
coded in Verilog by copying from existing work and that has worked pretty
well for me. But that was in a day job where I had people I could ask for
help if I didn't understand something and it only lasted a few months. To
use Verilog on my own I would want to be sure I wasn't embedding any time
bombs that would rear its ugly head after the design had been handed off to
a customer. Of course, that's always possible from logic errors, but I'm
talking about misuse of the language. I'd like a reference book that
clearly identifies these potential problems.

--

Rick C

Viewed the eclipse at Wintercrest Farms,
on the centerline of totality since 1998

BobH
Guest

Tue Jan 16, 2018 4:45 pm   



On 01/13/2018 02:28 PM, rickman wrote:
Quote:
BobH wrote on 1/13/2018 11:08 AM:
On 01/13/2018 12:57 AM, rickman wrote:
I met a guy in another forum who said not only he, but a number of
people
he has shown to use Verilog at work are much more productive.  I've
heard
that there are various defaults in Verilog that are real gotchas unless
you know about them.  But no one has been able to point me to a book
that
describes these issues.  Can you suggest a good Verilog book that covers
these details?  It doesn't have to be a beginner's book as I am pretty
experienced in HDL and have even done some work in Verilog.  I just want
to get to the point that I won't be making student mistakes in my
designs.  Well, at least no more than I do in VHDL.


The best Verilog reference book that I have found is "Verilog HDL A
Guide to
Digital Design and Synthesis" by Samir Palnitkar. It is good enough
that it
lives in my book bag to get hauled to work every day (and shows it now).
This is not really a beginners book, and it is not perfect, but it is the
best that I have found. There are at least two editions of this out and
there may be more. The second edition is the one that is most useful
to me.

For syntax questions, Stuart Sutherland's "Verilog HDL Quick Reference
Guide" is excellent. This document can be downloaded from Mr Sutherland's
web site. I work in Verilog and C depending on the phase of the
project that
I am in (FPGA or firmware). Swapping between Verilog and C means that
looking up the exact syntax is necessary, especially around the
transitions.

Do either of these books cover the defaults issue I mention above?  I
have coded in Verilog by copying from existing work and that has worked
pretty well for me.  But that was in a day job where I had people I
could ask for help if I didn't understand something and it only lasted a
few months.  To use Verilog on my own I would want to be sure I wasn't
embedding any time bombs that would rear its ugly head after the design
had been handed off to a customer.  Of course, that's always possible
from logic errors, but I'm talking about misuse of the language.  I'd
like a reference book that clearly identifies these potential problems.


I am not sure that there is a quick answer to what you are looking for.

Sutherland's Guide book is extremely short and tightly written (about 48
pages), it is written to provide quick answers on utilizing each
language element. While extremely useful, I don't think it will have the
answers you are looking for. You can download the whole thing for free
from his site:

http://sutherland-hdl.com/books_and_guides.html#V2K%20HDL%20Ref

and look for yourself. He has several other books including one
specifically on "gotchas" in Verilog and System Verilog that I have not
read. My start in Verilog was taking Sutherland's class in the late '90s
and his class text was clear and well written.

Palnitkar's book has details on usage of Verilog from basic to advanced
stuff. One of the main things that I use if for is understanding syntax
and behavior of "advanced" language elements from outside sources.

Kevin Neilson
Guest

Wed Jan 17, 2018 3:33 am   



Quote:
use Verilog on my own I would want to be sure I wasn't embedding any time
bombs that would rear its ugly head after the design had been handed off to
a customer. Of course, that's always possible from logic errors, but I'm
talking about misuse of the language. I'd like a reference book that
clearly identifies these potential problems.


Do you mean a misuse that would cause a mismatch between simulation and synthesis? The main type of issue I can think of that would "rear its head" later would be a clock-domain-crossing problem, but that wouldn't a result of misusing the language. If you forget to declare a multibit wire, it will be assumed that it's a single bit, and then you can have weird behavior because you thought it was a bus, but that's probably something you're going to quickly find in sim.

I do not think the Palnitkar book is good and I have never found any Verilog book that is very good. I have a decent one somewhere that is for engineers doing synthesis, though I can't remember the name, and it's more of a supplemental reference. You can find some papers on Cliff Cumming's Sunburst Design page which go over some Verilog solecisms.

rickman
Guest

Wed Jan 17, 2018 4:20 am   



Kevin Neilson wrote on 1/16/2018 8:33 PM:
Quote:

use Verilog on my own I would want to be sure I wasn't embedding any time
bombs that would rear its ugly head after the design had been handed off to
a customer. Of course, that's always possible from logic errors, but I'm
talking about misuse of the language. I'd like a reference book that
clearly identifies these potential problems.

Do you mean a misuse that would cause a mismatch between simulation and synthesis? The main type of issue I can think of that would "rear its head" later would be a clock-domain-crossing problem, but that wouldn't a result of misusing the language. If you forget to declare a multibit wire, it will be assumed that it's a single bit, and then you can have weird behavior because you thought it was a bus, but that's probably something you're going to quickly find in sim.


In VHDL everything is explicitly stated, no assumptions. In Verilog my
understanding is there are things that are assumed that you need to know
about or the tools will do something other than what you expect. It is not
possible to test everything, so some of these may be missed unless you are
wary of them. I don't recall anything about them, but I think some have to
do with arithmetic. In VHDL you specify the bus widths of operands, results
and even intermediates. I believe Verilog is consistent, but what it does
may not be obvious.


> I do not think the Palnitkar book is good and I have never found any Verilog book that is very good.

I get this a lot.


Quote:
I have a decent one somewhere that is for engineers doing synthesis, though I can't remember the name, and it's more of a supplemental reference. You can find some papers on Cliff Cumming's Sunburst Design page which go over some Verilog solecisms.



--

Rick C

Viewed the eclipse at Wintercrest Farms,
on the centerline of totality since 1998

o pere o
Guest

Wed Jan 17, 2018 9:37 am   



On 13/01/18 12:29, Thomas Heller wrote:
Quote:
Am 10.01.2018 um 15:17 schrieb john:

I'm trying to decide on which to use for a project as the main default that may
include a number of freelance people.

can you say which of these you actually use (the most)
and have the best skills in

Verilog
systemVerilog
SystemC
VHDL
Other


Is use MyHDL which gets translated into VHDL for synthesis.

Thomas


I had a look at MyHDL a while ago and it looked promising. Can you share
some experiences, pointers, etc? I'd like to know from someone who
actually is using it!

Pere

john p
Guest

Thu Jan 18, 2018 2:37 am   



On Tuesday, January 16, 2018 at 6:21:06 PM UTC-8, rickman wrote:
Quote:
Kevin Neilson wrote on 1/16/2018 8:33 PM:

use Verilog on my own I would want to be sure I wasn't embedding any time
bombs that would rear its ugly head after the design had been handed off to
a customer. Of course, that's always possible from logic errors, but I'm
talking about misuse of the language. I'd like a reference book that
clearly identifies these potential problems.

Do you mean a misuse that would cause a mismatch between simulation and synthesis? The main type of issue I can think of that would "rear its head" later would be a clock-domain-crossing problem, but that wouldn't a result of misusing the language. If you forget to declare a multibit wire, it will be assumed that it's a single bit, and then you can have weird behavior because you thought it was a bus, but that's probably something you're going to quickly find in sim.

In VHDL everything is explicitly stated, no assumptions. In Verilog my
understanding is there are things that are assumed that you need to know
about or the tools will do something other than what you expect. It is not
possible to test everything, so some of these may be missed unless you are
wary of them. I don't recall anything about them, but I think some have to
do with arithmetic. In VHDL you specify the bus widths of operands, results
and even intermediates. I believe Verilog is consistent, but what it does
may not be obvious.


I do not think the Palnitkar book is good and I have never found any Verilog book that is very good.

I get this a lot.


I have a decent one somewhere that is for engineers doing synthesis, though I can't remember the name, and it's more of a supplemental reference. You can find some papers on Cliff Cumming's Sunburst Design page which go over some Verilog solecisms.



--

Rick C

Viewed the eclipse at Wintercrest Farms,
on the centerline of totality since 1998


I have not yet found a Verilog book that I thought was worth buying :(

I'd look for papers by Sutherland and Cliff Cummings, especially, I think, Cliff's book on Verilog gotchas.

The key rule I use for Verilog is when coding combinatorial blocks, use
blocking assignments:
always @(*)
foo = bar;
When coding synchronous logic, use non-blocking assignments:
always @(posedge clk)
foo <= bar;

Rules are made to be broken, but I *rarely* break these two rules.

John P

Thomas Heller
Guest

Thu Jan 18, 2018 10:31 am   



Am 17.01.2018 um 08:37 schrieb o pere o:
Quote:
On 13/01/18 12:29, Thomas Heller wrote:
Am 10.01.2018 um 15:17 schrieb john:

can you say which of these you actually use (the most)
and have the best skills in

Verilog
systemVerilog
SystemC
VHDL
Other


Is use MyHDL which gets translated into VHDL for synthesis.


I had a look at MyHDL a while ago and it looked promising. Can you share
some experiences, pointers, etc? I'd like to know from someone who
actually is using it!


I'm not good at writing reviews, but I'm very happy with MyHDL. It
removes the pain that I mostly feel when writing VHDL.
And using MyHDL is the first time that I write real testbenches
and simulate.

Something that I can recommend to read about MyHDL are articles by Jan
Decaluwe, the main author, at http://jandecaluwe.com/hdldesign/ .
Especially this one: http://jandecaluwe.com/hdldesign/counting.html .
Then Christopher Felton also has a couple of nice articles at
fpgarelated:
https://www.fpgarelated.com/blogs-1/nf/Christopher_Felton.php

Thomas

Mark Humphries
Guest

Thu Jan 18, 2018 5:34 pm   



On Wednesday, January 10, 2018 at 10:17:32 PM UTC+8, john wrote:
Quote:
I'm trying to decide on which to use for a project as the main default that may
include a number of freelance people.

can you say which of these you actually use (the most)
and have the best skills in

Verilog
systemVerilog
SystemC
VHDL
Other

And if possible what type of work you use it for in general
I dont need to know why you use a particular one - and to avoid
flame wars request you dont explain that.

I'm just trying to get a general feel for what people here use regularly.

TIA

--

john

=========================
http://johntech.co.uk
=========================


I've recently switched from Verilog 2001 to SystemVerilog, fewer gotchas to work around.

For a reference I recommend:
RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design by Stuart Sutherland.

rickman
Guest

Thu Jan 18, 2018 5:53 pm   



Mark Humphries wrote on 1/18/2018 10:34 AM:
Quote:
On Wednesday, January 10, 2018 at 10:17:32 PM UTC+8, john wrote:
I'm trying to decide on which to use for a project as the main default that may
include a number of freelance people.

can you say which of these you actually use (the most)
and have the best skills in

Verilog
systemVerilog
SystemC
VHDL
Other

And if possible what type of work you use it for in general
I dont need to know why you use a particular one - and to avoid
flame wars request you dont explain that.

I'm just trying to get a general feel for what people here use regularly.

TIA

--

john

=========================
http://johntech.co.uk
=========================

I've recently switched from Verilog 2001 to SystemVerilog, fewer gotchas to work around.

For a reference I recommend:
RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design by Stuart Sutherland.


Seems to be a $120 book. That's a bit steep even for HDL books.

--

Rick C

Viewed the eclipse at Wintercrest Farms,
on the centerline of totality since 1998

Theo Markettos
Guest

Thu Jan 18, 2018 6:46 pm   



john <anon_at_example.com> wrote:
Quote:

I'm trying to decide on which to use for a project as the main default
that may include a number of freelance people.

can you say which of these you actually use (the most)
and have the best skills in


Bluespec SystemVerilog (BSV), which is actually nothing to do with
SystemVerilog but is a high-level HDL derived from Haskell (including types,
polymorphism, functional language features).

Since BSV is a bit niche, I teach SystemVerilog to undergrads and will use
it for glue when necessary.

Talking to major IP vendors who provide both Verilog and VHDL versions of
IP, the Verilog versions are a lot more popular.

Theo

HT-Lab
Guest

Tue Jan 23, 2018 9:30 pm   



On 10/01/2018 20:29, already5chosen_at_yahoo.com wrote:
Quote:
On Wednesday, January 10, 2018 at 7:33:10 PM UTC+2, Rob Gaddi wrote:
On 01/10/2018 06:17 AM, john wrote:
...


VHDL, for both synthesis and testbenching. Some Verilog sneaks into my
design when vendor-provided IP cores only come that way, but I'm
read-only on it.

--
Rob Gaddi, Highland Technology -- www.highlandtechnology.com
Email address domain is currently out of order. See above to fix.

The same here.
And I don't believe in things like SystemC.


I do.

It is true SystemC is more for the C/C++ aficionados. However SystemC
has a lot going for it, here are some quick points:

1) You get a simulator and all the support libraries in source for free.
2) If you know VHDL then you can easily program in SystemC (same model
of signals, processes, variables, delta cycles etc). No horrible
blocking/non-blocking, wire/reg, race spaghetti.
3) It is easy to learn and you don't have to dive to deep into C++.
4) It is great for behavioural modelling.
5) You can choose from many free and commercial IDE's.
6) There is a free UVM library.
7) It runs on many platforms (you just need a C++ compiler)
Cool There is a synthesisable standard (albeit somewhat outdated)
9) There are a number of SystemC translators/synthesis tools available.
10) You can "embed" the OSCI engine into your product (bar the usual
license agreement)
11) It is relative easy to bolt on any library you like Qt/SDL2.
12) It has the best TLM capabilities (SV uses the same models)
13) It has transaction recordings capabilities (SCV)
14) It has some assertion capabilities (PSL support would be great!)
15) It supports randomisation (like rand in SV) and contains a
constraint solver.

The free nature of it is both a blessing and a curse. Because it is free
commercial support is somewhat sluggish (Cadence being the exception).
There are (AFAIK) no free RTL style IDE's which works as easily as
VHDL/Verilog on Modelsim/VCS/NCSim/Riviera/etc. Using sc_trace and
GTKWave is just too painful. There are products like Vista that come
close but still not as slick as Modelsim. I tried to write something but
underestimated the amount of free time it takes to create something
barely usable.

So for pure RTL designs I agree that you can't beat good old VHDL and SV
(forget about Verilog).

To answer the OP's question, VHDL for design and
VHDL/SystemC/PSL/FLI/Tcl for testbenches. I do try to keep up with SV as
a good engineer needs to know both.

Regards,
Hans
www.ht-lab.com


Guest

Mon Feb 12, 2018 11:08 am   



W dniu środa, 10 stycznia 2018 15:17:32 UTC+1 użytkownik john napisał:
Quote:
I'm trying to decide on which to use for a project as the main default that may
include a number of freelance people.

can you say which of these you actually use (the most)
and have the best skills in

Verilog
systemVerilog
SystemC
VHDL
Other

And if possible what type of work you use it for in general
I dont need to know why you use a particular one - and to avoid
flame wars request you dont explain that.

I'm just trying to get a general feel for what people here use regularly.

TIA

--

john

========================> http://johntech.co.uk
========================

I use mainly VHDL (I often design complex data acquisition and processing system and havily use VHDL records to describe complex data structures)
I'm trying to use systemVerilog

BR,
Wojtek

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