Have anyone used the "justify" function successfully in ques

Wed Feb 10, 2010 3:33 pm   

Hi,

when I try to use the justify function inside a write statement it
always produces garbage output.

E.g:

variable i : integer := 10;
....
write(tbuf, "Value is " & justify(to_string(i), field => ));
writeline(output, tbuf);

Also, I have a problem with the to_hstring function for
std_logic_vectors. I doesn't accept slv so I have to convert my slv to
bit_vector first, which I find to be annoying. And my sim log will show
0000... when the actual result was UUUU... etc.

I usually use hwrite instead, but it results in several more lines of code.

Have any of you had more success using these new language features?

Magne

Wed Feb 10, 2010 4:03 pm   

Magne Munkejord wrote:

It works fine for me on Questa 6.5d

What do you mean by "garbage"? Not the value -2147483648 I hope :-)


I can't find any implementations of to_hstring in 6.5d (unless I'm
looking in the wrong place?).

What package is your to_hstring for bit_vector? Which version of Questa
are you using?

regards
Alan





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Wed Feb 10, 2010 4:32 pm   

Alan Fitch wrote:

Nope, garbage like this :
# Value is D’~€m

it doesn't even copy-paste correctly.


I think the implementations these functions in questasim is
accellerated/encrypted. That is what it says in the package, anyways. So
we can't look at the source code.

I use questa 6.5c. Guess I will go get the upgrade then ;)

Below is the code I used for testing. It compiles and runs producing
this output:
# Value is Ìó~
# Hex value is A5

maybe you could try to uncomment the line where I tried to use
to_hstring directly on the slv.

use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
--use ieee.std_logic_textio.all;

entity ett is end entity ett;

architecture att of ett is
begin
ptt : process is
variable i : integer := 10;
variable tbuf : line;
variable vec : std_logic_vector(7 downto 0) := X"A5";
begin
write(tbuf, "Value is " & justify(to_string(i), field => );
writeline(output, tbuf);
--write(tbuf, "Hex value is " & to_hstring(vec));
write(tbuf, "Hex value is " & to_hstring(to_bitvector(vec)));
writeline(output, tbuf);
wait;
end process ptt;

end architecture att;

Wed Feb 10, 2010 4:56 pm   

Magne Munkejord wrote:

functions are implicitly declared at the end of the std.standard package
for bit_vector (see page 51). But on page 50 it says that such functions
are implicitly declared for any one dimensional array type of character
literals - so there should be versions for std_logic_vector which I
guess should be implicitly declared inside std_logic_1164.


I think that might help. I will try out your code as well.


OK I'll have a go.

regards
Alan


--
Alan Fitch
Senior Consultant

Doulos – Developing Design Know-how
VHDL * Verilog * SystemVerilog * SystemC * PSL * Perl * Tcl/Tk * Project
Services

Doulos Ltd. Church Hatch, 22 Marketing Place, Ringwood, Hampshire, BH24
1AW, UK
Tel: + 44 (0)1425 471223 Email: alan.fitch_at_doulos.com
Fax: +44 (0)1425 471573 http://www.doulos.com

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Wed Feb 10, 2010 5:01 pm   

Magne Munkejord wrote:
<snip>





I guess it's an unimplemented feature? You'd have to ask Mentor,

regards
Alan

P.S. I am downloading 6.6 to see if that helps...



--
Alan Fitch
Senior Consultant

Doulos – Developing Design Know-how
VHDL * Verilog * SystemVerilog * SystemC * PSL * Perl * Tcl/Tk * Project
Services

Doulos Ltd. Church Hatch, 22 Marketing Place, Ringwood, Hampshire, BH24
1AW, UK
Tel: + 44 (0)1425 471223 Email: alan.fitch_at_doulos.com
Fax: +44 (0)1425 471573 http://www.doulos.com

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Wed Feb 10, 2010 5:51 pm   

Alan Fitch wrote:

And it doesn't work in 6.6 either,

Alan




--
Alan Fitch
Senior Consultant

Doulos – Developing Design Know-how
VHDL * Verilog * SystemVerilog * SystemC * PSL * Perl * Tcl/Tk * Project
Services

Doulos Ltd. Church Hatch, 22 Marketing Place, Ringwood, Hampshire, BH24
1AW, UK
Tel: + 44 (0)1425 471223 Email: alan.fitch_at_doulos.com
Fax: +44 (0)1425 471573 http://www.doulos.com

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Thu Feb 11, 2010 3:25 am   

Alan Fitch wrote:

Sounds like I'll have to run my test cases through 6.6.
You will find VHDL-93 compatible code for this function here:
http://www.vhdl.org/fphdl