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bitrex
Guest

Fri May 01, 2020 7:45 pm   



Here's the situation in simplified schematic form, generate a
high-efficiency sine wave at around 3-5MHz putting out about 5 watts
into resistive load:

<https://www.dropbox.com/s/tz1zp0d8oy8zkws/IMG_20200501_133832793.jpg?dl=0>

Just drive it like two half-bridges with appropriate logic-level
wavaeforms (some dead-time) and if you look at the two switching nodes
together on a plot you get the red/black waveform there under inductor
L1. LC filter it through a coupled inductor. and Bob's your Dad's uncle.
in theory.

First attempt at it on a protoboard:

<https://www.dropbox.com/s/1n69o0yzhd2rbpk/Schem.PNG?dl=0>

"it looks great in the sim" and the connection of the boost diodes to
the switching nodes gives a nice ~12-13 volt Vdd to common rail above
the lockout threshold for the flying driver's supply nodes and keeps all
the component dissipation low.

<https://www.dropbox.com/s/sv5fox0ywcmpypv/Sine.PNG?dl=0>

Total miserable nightmare to get working right as a prototype, losing
gate drivers for unknown reason, these chips seem way slower than the
~50n prop delay specified in the datasheet, can't get up to speed. I
don't think this 4120 likes being driven the way it's connected here in
reality and they're dying on me, or I've made an error in the
implementation somewhere i can't readily spot.

Anyway, I hate it, looking for any suggestions or alternate gate-drive
schemes for this, I'd like a cheaper faster and more rugged one, as
someone mentioned I don't really need the ADuM4120's internal
transformer isolation if I could find a good way to level-shift the
incoming logic level drive appropriately to the negative rails the lower
FETs have. Thanks

John Larkin
Guest

Fri May 01, 2020 8:45 pm   



On Fri, 1 May 2020 15:08:07 -0400, bitrex <user_at_example.net> wrote:

Quote:
On 5/1/2020 2:47 PM, John Larkin wrote:
On Fri, 1 May 2020 14:03:15 -0400, bitrex <user_at_example.net> wrote:

Here's the situation in simplified schematic form, generate a
high-efficiency sine wave at around 3-5MHz putting out about 5 watts
into resistive load:

https://www.dropbox.com/s/tz1zp0d8oy8zkws/IMG_20200501_133832793.jpg?dl=0

Just drive it like two half-bridges with appropriate logic-level
wavaeforms (some dead-time) and if you look at the two switching nodes
together on a plot you get the red/black waveform there under inductor
L1. LC filter it through a coupled inductor. and Bob's your Dad's uncle.
in theory.

First attempt at it on a protoboard:

https://www.dropbox.com/s/1n69o0yzhd2rbpk/Schem.PNG?dl=0

"it looks great in the sim" and the connection of the boost diodes to
the switching nodes gives a nice ~12-13 volt Vdd to common rail above
the lockout threshold for the flying driver's supply nodes and keeps all
the component dissipation low.

https://www.dropbox.com/s/sv5fox0ywcmpypv/Sine.PNG?dl=0

Total miserable nightmare to get working right as a prototype, losing
gate drivers for unknown reason, these chips seem way slower than the
~50n prop delay specified in the datasheet, can't get up to speed. I
don't think this 4120 likes being driven the way it's connected here in
reality and they're dying on me, or I've made an error in the
implementation somewhere i can't readily spot.

Anyway, I hate it, looking for any suggestions or alternate gate-drive
schemes for this, I'd like a cheaper faster and more rugged one, as
someone mentioned I don't really need the ADuM4120's internal
transformer isolation if I could find a good way to level-shift the
incoming logic level drive appropriately to the negative rails the lower
FETs have. Thanks

I can envision a lot of DC circulating in addition to switching
losses.

This will be difficult with mosfets and regular gate drivers, as you
note. You might consider something simpler, like a single mosfet or
SiC fet in a tuned class-C amp. RF stuff. One power part on a heat
sink.

You could probably use some gate drivers, like IXDN602, as the output
device itself if all you need is 5 watts. They are cheap and fast and
handy for a lot more than gate driving.


Huh. That's an interesting chip. Goes up to 35 input, too. Wonder if
they'd like being paralleled...


Data sheet says yes.

Two, or maybe 4, of them would be no big deal in space or cost.



Quote:

This is my second idea for KISS-approach:

https://www.dropbox.com/s/dewy6eqpggoagg5/IMG_20200501_145539343.jpg?dl=0

Use two non-isolated gate driver chips with like 10ns propagation delay.
One of two shown. Keep the flying-boostrap connection the same. And
"level shift" simply by capactively coupling the logic inputs.

It needs an extra two regulators to make a Vcc appropriately above the
negative supplies on the primary side. But I think it's better than
messing with four isolated drivers, I don't really need them for
isolation just level-shifting.


How about a single half-bridge? Step up the voltage passively if you
need to, transformer or resonant circuit.

We make simple transmission-line transformers, 2:1 step-up at 100
volts pulse out into 50 ohms and maybe 1 ns rise time.

--

John Larkin Highland Technology, Inc
picosecond timing precision measurement

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

bitrex
Guest

Fri May 01, 2020 8:45 pm   



On 5/1/2020 3:08 PM, bitrex wrote:
Quote:
On 5/1/2020 2:47 PM, John Larkin wrote:
On Fri, 1 May 2020 14:03:15 -0400, bitrex <user_at_example.net> wrote:

Here's the situation in simplified schematic form, generate a
high-efficiency sine wave at around 3-5MHz putting out about 5 watts
into resistive load:

https://www.dropbox.com/s/tz1zp0d8oy8zkws/IMG_20200501_133832793.jpg?dl=0


Just drive it like two half-bridges with appropriate logic-level
wavaeforms (some dead-time) and if you look at the two switching nodes
together on a plot you get the red/black waveform there under inductor
L1. LC filter it through a coupled inductor. and Bob's your Dad's uncle.
in theory.

First attempt at it on a protoboard:

https://www.dropbox.com/s/1n69o0yzhd2rbpk/Schem.PNG?dl=0

"it looks great in the sim" and the connection of the boost diodes to
the switching nodes gives a nice ~12-13 volt Vdd to common rail above
the lockout threshold for the flying driver's supply nodes and keeps all
the component dissipation low.

https://www.dropbox.com/s/sv5fox0ywcmpypv/Sine.PNG?dl=0

Total miserable nightmare to get working right as a prototype, losing
gate drivers for unknown reason, these chips seem way slower than the
~50n prop delay specified in the datasheet, can't get up to speed. I
don't think this 4120 likes being driven the way it's connected here in
reality and they're dying on me, or I've made an error in the
implementation somewhere i can't readily spot.

Anyway, I hate it, looking for any suggestions or alternate gate-drive
schemes for this, I'd like a cheaper faster and more rugged one, as
someone mentioned I don't really need the ADuM4120's internal
transformer isolation if I could find a good way to level-shift the
incoming logic level drive appropriately to the negative rails the lower
FETs have. Thanks

I can envision a lot of DC circulating in addition to switching
losses.

This will be difficult with mosfets and regular gate drivers, as you
note. You might consider something simpler, like a single mosfet or
SiC fet in a tuned class-C amp. RF stuff. One power part on a heat
sink.

You could probably use some gate drivers, like IXDN602, as the output
device itself if all you need is 5 watts. They are cheap and fast and
handy for a lot more than gate driving.


Huh. That's an interesting chip. Goes up to 35 input, too. Wonder if
they'd like being paralleled...

This is my second idea for KISS-approach:

https://www.dropbox.com/s/dewy6eqpggoagg5/IMG_20200501_145539343.jpg?dl=0

Use two non-isolated gate driver chips with like 10ns propagation delay.
One of two shown. Keep the flying-boostrap connection the same. And
"level shift" simply by capactively coupling the logic inputs.

It needs an extra two regulators to make a Vcc appropriately above the
negative supplies on the primary side. But I think it's better than
messing with four isolated drivers, I don't really need them for
isolation just level-shifting.


Oops, forgot to connect "HS" to the mid-point in that diagram

bitrex
Guest

Fri May 01, 2020 8:45 pm   



On 5/1/2020 2:47 PM, John Larkin wrote:
Quote:
On Fri, 1 May 2020 14:03:15 -0400, bitrex <user_at_example.net> wrote:

Here's the situation in simplified schematic form, generate a
high-efficiency sine wave at around 3-5MHz putting out about 5 watts
into resistive load:

https://www.dropbox.com/s/tz1zp0d8oy8zkws/IMG_20200501_133832793.jpg?dl=0

Just drive it like two half-bridges with appropriate logic-level
wavaeforms (some dead-time) and if you look at the two switching nodes
together on a plot you get the red/black waveform there under inductor
L1. LC filter it through a coupled inductor. and Bob's your Dad's uncle.
in theory.

First attempt at it on a protoboard:

https://www.dropbox.com/s/1n69o0yzhd2rbpk/Schem.PNG?dl=0

"it looks great in the sim" and the connection of the boost diodes to
the switching nodes gives a nice ~12-13 volt Vdd to common rail above
the lockout threshold for the flying driver's supply nodes and keeps all
the component dissipation low.

https://www.dropbox.com/s/sv5fox0ywcmpypv/Sine.PNG?dl=0

Total miserable nightmare to get working right as a prototype, losing
gate drivers for unknown reason, these chips seem way slower than the
~50n prop delay specified in the datasheet, can't get up to speed. I
don't think this 4120 likes being driven the way it's connected here in
reality and they're dying on me, or I've made an error in the
implementation somewhere i can't readily spot.

Anyway, I hate it, looking for any suggestions or alternate gate-drive
schemes for this, I'd like a cheaper faster and more rugged one, as
someone mentioned I don't really need the ADuM4120's internal
transformer isolation if I could find a good way to level-shift the
incoming logic level drive appropriately to the negative rails the lower
FETs have. Thanks

I can envision a lot of DC circulating in addition to switching
losses.


I think the flying-diode connection to the opposing switching nodes
helps there with negative feedback. If one side develops a DC-offset the
boost gate-drive voltage on the opposing side increases or decreases to
push it back

bitrex
Guest

Fri May 01, 2020 8:45 pm   



On 5/1/2020 2:47 PM, John Larkin wrote:
Quote:
On Fri, 1 May 2020 14:03:15 -0400, bitrex <user_at_example.net> wrote:

Here's the situation in simplified schematic form, generate a
high-efficiency sine wave at around 3-5MHz putting out about 5 watts
into resistive load:

https://www.dropbox.com/s/tz1zp0d8oy8zkws/IMG_20200501_133832793.jpg?dl=0

Just drive it like two half-bridges with appropriate logic-level
wavaeforms (some dead-time) and if you look at the two switching nodes
together on a plot you get the red/black waveform there under inductor
L1. LC filter it through a coupled inductor. and Bob's your Dad's uncle.
in theory.

First attempt at it on a protoboard:

https://www.dropbox.com/s/1n69o0yzhd2rbpk/Schem.PNG?dl=0

"it looks great in the sim" and the connection of the boost diodes to
the switching nodes gives a nice ~12-13 volt Vdd to common rail above
the lockout threshold for the flying driver's supply nodes and keeps all
the component dissipation low.

https://www.dropbox.com/s/sv5fox0ywcmpypv/Sine.PNG?dl=0

Total miserable nightmare to get working right as a prototype, losing
gate drivers for unknown reason, these chips seem way slower than the
~50n prop delay specified in the datasheet, can't get up to speed. I
don't think this 4120 likes being driven the way it's connected here in
reality and they're dying on me, or I've made an error in the
implementation somewhere i can't readily spot.

Anyway, I hate it, looking for any suggestions or alternate gate-drive
schemes for this, I'd like a cheaper faster and more rugged one, as
someone mentioned I don't really need the ADuM4120's internal
transformer isolation if I could find a good way to level-shift the
incoming logic level drive appropriately to the negative rails the lower
FETs have. Thanks

I can envision a lot of DC circulating in addition to switching
losses.

This will be difficult with mosfets and regular gate drivers, as you
note. You might consider something simpler, like a single mosfet or
SiC fet in a tuned class-C amp. RF stuff. One power part on a heat
sink.

You could probably use some gate drivers, like IXDN602, as the output
device itself if all you need is 5 watts. They are cheap and fast and
handy for a lot more than gate driving.


Huh. That's an interesting chip. Goes up to 35 input, too. Wonder if
they'd like being paralleled...

This is my second idea for KISS-approach:

<https://www.dropbox.com/s/dewy6eqpggoagg5/IMG_20200501_145539343.jpg?dl=0>

Use two non-isolated gate driver chips with like 10ns propagation delay.
One of two shown. Keep the flying-boostrap connection the same. And
"level shift" simply by capactively coupling the logic inputs.

It needs an extra two regulators to make a Vcc appropriately above the
negative supplies on the primary side. But I think it's better than
messing with four isolated drivers, I don't really need them for
isolation just level-shifting.

John Larkin
Guest

Fri May 01, 2020 8:45 pm   



On Fri, 1 May 2020 14:03:15 -0400, bitrex <user_at_example.net> wrote:

Quote:
Here's the situation in simplified schematic form, generate a
high-efficiency sine wave at around 3-5MHz putting out about 5 watts
into resistive load:

https://www.dropbox.com/s/tz1zp0d8oy8zkws/IMG_20200501_133832793.jpg?dl=0

Just drive it like two half-bridges with appropriate logic-level
wavaeforms (some dead-time) and if you look at the two switching nodes
together on a plot you get the red/black waveform there under inductor
L1. LC filter it through a coupled inductor. and Bob's your Dad's uncle.
in theory.

First attempt at it on a protoboard:

https://www.dropbox.com/s/1n69o0yzhd2rbpk/Schem.PNG?dl=0

"it looks great in the sim" and the connection of the boost diodes to
the switching nodes gives a nice ~12-13 volt Vdd to common rail above
the lockout threshold for the flying driver's supply nodes and keeps all
the component dissipation low.

https://www.dropbox.com/s/sv5fox0ywcmpypv/Sine.PNG?dl=0

Total miserable nightmare to get working right as a prototype, losing
gate drivers for unknown reason, these chips seem way slower than the
~50n prop delay specified in the datasheet, can't get up to speed. I
don't think this 4120 likes being driven the way it's connected here in
reality and they're dying on me, or I've made an error in the
implementation somewhere i can't readily spot.

Anyway, I hate it, looking for any suggestions or alternate gate-drive
schemes for this, I'd like a cheaper faster and more rugged one, as
someone mentioned I don't really need the ADuM4120's internal
transformer isolation if I could find a good way to level-shift the
incoming logic level drive appropriately to the negative rails the lower
FETs have. Thanks


I can envision a lot of DC circulating in addition to switching
losses.

This will be difficult with mosfets and regular gate drivers, as you
note. You might consider something simpler, like a single mosfet or
SiC fet in a tuned class-C amp. RF stuff. One power part on a heat
sink.

You could probably use some gate drivers, like IXDN602, as the output
device itself if all you need is 5 watts. They are cheap and fast and
handy for a lot more than gate driving.

--

John Larkin Highland Technology, Inc
picosecond timing precision measurement

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

John Larkin
Guest

Fri May 01, 2020 8:45 pm   



On Fri, 1 May 2020 15:17:11 -0400, bitrex <user_at_example.net> wrote:

Quote:
On 5/1/2020 2:47 PM, John Larkin wrote:
On Fri, 1 May 2020 14:03:15 -0400, bitrex <user_at_example.net> wrote:

Here's the situation in simplified schematic form, generate a
high-efficiency sine wave at around 3-5MHz putting out about 5 watts
into resistive load:

https://www.dropbox.com/s/tz1zp0d8oy8zkws/IMG_20200501_133832793.jpg?dl=0

Just drive it like two half-bridges with appropriate logic-level
wavaeforms (some dead-time) and if you look at the two switching nodes
together on a plot you get the red/black waveform there under inductor
L1. LC filter it through a coupled inductor. and Bob's your Dad's uncle.
in theory.

First attempt at it on a protoboard:

https://www.dropbox.com/s/1n69o0yzhd2rbpk/Schem.PNG?dl=0

"it looks great in the sim" and the connection of the boost diodes to
the switching nodes gives a nice ~12-13 volt Vdd to common rail above
the lockout threshold for the flying driver's supply nodes and keeps all
the component dissipation low.

https://www.dropbox.com/s/sv5fox0ywcmpypv/Sine.PNG?dl=0

Total miserable nightmare to get working right as a prototype, losing
gate drivers for unknown reason, these chips seem way slower than the
~50n prop delay specified in the datasheet, can't get up to speed. I
don't think this 4120 likes being driven the way it's connected here in
reality and they're dying on me, or I've made an error in the
implementation somewhere i can't readily spot.

Anyway, I hate it, looking for any suggestions or alternate gate-drive
schemes for this, I'd like a cheaper faster and more rugged one, as
someone mentioned I don't really need the ADuM4120's internal
transformer isolation if I could find a good way to level-shift the
incoming logic level drive appropriately to the negative rails the lower
FETs have. Thanks

I can envision a lot of DC circulating in addition to switching
losses.

I think the flying-diode connection to the opposing switching nodes
helps there with negative feedback. If one side develops a DC-offset the
boost gate-drive voltage on the opposing side increases or decreases to
push it back


Or add a capacitor!

--

John Larkin Highland Technology, Inc
picosecond timing precision measurement

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

John Larkin
Guest

Fri May 01, 2020 9:45 pm   



On Fri, 1 May 2020 15:45:45 -0400, bitrex <user_at_example.net> wrote:

Quote:
On 5/1/2020 3:40 PM, John Larkin wrote:
On Fri, 1 May 2020 15:17:11 -0400, bitrex <user_at_example.net> wrote:

On 5/1/2020 2:47 PM, John Larkin wrote:
On Fri, 1 May 2020 14:03:15 -0400, bitrex <user_at_example.net> wrote:

Here's the situation in simplified schematic form, generate a
high-efficiency sine wave at around 3-5MHz putting out about 5 watts
into resistive load:

https://www.dropbox.com/s/tz1zp0d8oy8zkws/IMG_20200501_133832793.jpg?dl=0

Just drive it like two half-bridges with appropriate logic-level
wavaeforms (some dead-time) and if you look at the two switching nodes
together on a plot you get the red/black waveform there under inductor
L1. LC filter it through a coupled inductor. and Bob's your Dad's uncle.
in theory.

First attempt at it on a protoboard:

https://www.dropbox.com/s/1n69o0yzhd2rbpk/Schem.PNG?dl=0

"it looks great in the sim" and the connection of the boost diodes to
the switching nodes gives a nice ~12-13 volt Vdd to common rail above
the lockout threshold for the flying driver's supply nodes and keeps all
the component dissipation low.

https://www.dropbox.com/s/sv5fox0ywcmpypv/Sine.PNG?dl=0

Total miserable nightmare to get working right as a prototype, losing
gate drivers for unknown reason, these chips seem way slower than the
~50n prop delay specified in the datasheet, can't get up to speed. I
don't think this 4120 likes being driven the way it's connected here in
reality and they're dying on me, or I've made an error in the
implementation somewhere i can't readily spot.

Anyway, I hate it, looking for any suggestions or alternate gate-drive
schemes for this, I'd like a cheaper faster and more rugged one, as
someone mentioned I don't really need the ADuM4120's internal
transformer isolation if I could find a good way to level-shift the
incoming logic level drive appropriately to the negative rails the lower
FETs have. Thanks

I can envision a lot of DC circulating in addition to switching
losses.

I think the flying-diode connection to the opposing switching nodes
helps there with negative feedback. If one side develops a DC-offset the
boost gate-drive voltage on the opposing side increases or decreases to
push it back


Or add a capacitor!

Where, in line with the Ls?


Yes.

Even a small duty cycle mismatch could pump a lot of DC current
through those inductors.

--

John Larkin Highland Technology, Inc
picosecond timing precision measurement

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

bitrex
Guest

Fri May 01, 2020 9:45 pm   



On 5/1/2020 4:41 PM, bitrex wrote:
Quote:
On 5/1/2020 4:21 PM, John Larkin wrote:
On Fri, 1 May 2020 15:45:45 -0400, bitrex <user_at_example.net> wrote:

On 5/1/2020 3:40 PM, John Larkin wrote:
On Fri, 1 May 2020 15:17:11 -0400, bitrex <user_at_example.net> wrote:

On 5/1/2020 2:47 PM, John Larkin wrote:
On Fri, 1 May 2020 14:03:15 -0400, bitrex <user_at_example.net> wrote:

Here's the situation in simplified schematic form, generate a
high-efficiency sine wave at around 3-5MHz putting out about 5 watts
into resistive load:

https://www.dropbox.com/s/tz1zp0d8oy8zkws/IMG_20200501_133832793.jpg?dl=0


Just drive it like two half-bridges with appropriate logic-level
wavaeforms (some dead-time) and if you look at the two switching
nodes
together on a plot you get the red/black waveform there under
inductor
L1. LC filter it through a coupled inductor. and Bob's your Dad's
uncle.
in theory.

First attempt at it on a protoboard:

https://www.dropbox.com/s/1n69o0yzhd2rbpk/Schem.PNG?dl=0

"it looks great in the sim" and the connection of the boost
diodes to
the switching nodes gives a nice ~12-13 volt Vdd to common rail
above
the lockout threshold for the flying driver's supply nodes and
keeps all
the component dissipation low.

https://www.dropbox.com/s/sv5fox0ywcmpypv/Sine.PNG?dl=0

Total miserable nightmare to get working right as a prototype,
losing
gate drivers for unknown reason, these chips seem way slower than
the
~50n prop delay specified in the datasheet, can't get up to speed. I
don't think this 4120 likes being driven the way it's connected
here in
reality and they're dying on me, or I've made an error in the
implementation somewhere i can't readily spot.

Anyway, I hate it, looking for any suggestions or alternate
gate-drive
schemes for this, I'd like a cheaper faster and more rugged one, as
someone mentioned I don't really need the ADuM4120's internal
transformer isolation if I could find a good way to level-shift the
incoming logic level drive appropriately to the negative rails
the lower
FETs have. Thanks

I can envision a lot of DC circulating in addition to switching
losses.

I think the flying-diode connection to the opposing switching nodes
helps there with negative feedback. If one side develops a
DC-offset the
boost gate-drive voltage on the opposing side increases or
decreases to
push it back


Or add a capacitor!

Where, in line with the Ls?

Yes.

Even a small duty cycle mismatch could pump a lot of DC current
through those inductors.


I'll check if that stops it trashing gate drivers at least, the output
stage can handle a bit of offset but it does look like the more fragile
gate-driver FETs are going to be unhappy with that. They're
thermally-limited but it probably can't react fast enough to big
offset-related spikes. Sad


The AD devices and FETs are too well-matched in the sim and as such the
DC-problem doesn't obviously rear up.

bitrex
Guest

Fri May 01, 2020 9:45 pm   



On 5/1/2020 4:21 PM, John Larkin wrote:
Quote:
On Fri, 1 May 2020 15:45:45 -0400, bitrex <user_at_example.net> wrote:

On 5/1/2020 3:40 PM, John Larkin wrote:
On Fri, 1 May 2020 15:17:11 -0400, bitrex <user_at_example.net> wrote:

On 5/1/2020 2:47 PM, John Larkin wrote:
On Fri, 1 May 2020 14:03:15 -0400, bitrex <user_at_example.net> wrote:

Here's the situation in simplified schematic form, generate a
high-efficiency sine wave at around 3-5MHz putting out about 5 watts
into resistive load:

https://www.dropbox.com/s/tz1zp0d8oy8zkws/IMG_20200501_133832793.jpg?dl=0

Just drive it like two half-bridges with appropriate logic-level
wavaeforms (some dead-time) and if you look at the two switching nodes
together on a plot you get the red/black waveform there under inductor
L1. LC filter it through a coupled inductor. and Bob's your Dad's uncle.
in theory.

First attempt at it on a protoboard:

https://www.dropbox.com/s/1n69o0yzhd2rbpk/Schem.PNG?dl=0

"it looks great in the sim" and the connection of the boost diodes to
the switching nodes gives a nice ~12-13 volt Vdd to common rail above
the lockout threshold for the flying driver's supply nodes and keeps all
the component dissipation low.

https://www.dropbox.com/s/sv5fox0ywcmpypv/Sine.PNG?dl=0

Total miserable nightmare to get working right as a prototype, losing
gate drivers for unknown reason, these chips seem way slower than the
~50n prop delay specified in the datasheet, can't get up to speed. I
don't think this 4120 likes being driven the way it's connected here in
reality and they're dying on me, or I've made an error in the
implementation somewhere i can't readily spot.

Anyway, I hate it, looking for any suggestions or alternate gate-drive
schemes for this, I'd like a cheaper faster and more rugged one, as
someone mentioned I don't really need the ADuM4120's internal
transformer isolation if I could find a good way to level-shift the
incoming logic level drive appropriately to the negative rails the lower
FETs have. Thanks

I can envision a lot of DC circulating in addition to switching
losses.

I think the flying-diode connection to the opposing switching nodes
helps there with negative feedback. If one side develops a DC-offset the
boost gate-drive voltage on the opposing side increases or decreases to
push it back


Or add a capacitor!

Where, in line with the Ls?

Yes.

Even a small duty cycle mismatch could pump a lot of DC current
through those inductors.


I'll check if that stops it trashing gate drivers at least, the output
stage can handle a bit of offset but it does look like the more fragile
gate-driver FETs are going to be unhappy with that. They're
thermally-limited but it probably can't react fast enough to big
offset-related spikes. Sad

bitrex
Guest

Fri May 01, 2020 9:45 pm   



On 5/1/2020 3:40 PM, John Larkin wrote:
Quote:
On Fri, 1 May 2020 15:17:11 -0400, bitrex <user_at_example.net> wrote:

On 5/1/2020 2:47 PM, John Larkin wrote:
On Fri, 1 May 2020 14:03:15 -0400, bitrex <user_at_example.net> wrote:

Here's the situation in simplified schematic form, generate a
high-efficiency sine wave at around 3-5MHz putting out about 5 watts
into resistive load:

https://www.dropbox.com/s/tz1zp0d8oy8zkws/IMG_20200501_133832793.jpg?dl=0

Just drive it like two half-bridges with appropriate logic-level
wavaeforms (some dead-time) and if you look at the two switching nodes
together on a plot you get the red/black waveform there under inductor
L1. LC filter it through a coupled inductor. and Bob's your Dad's uncle.
in theory.

First attempt at it on a protoboard:

https://www.dropbox.com/s/1n69o0yzhd2rbpk/Schem.PNG?dl=0

"it looks great in the sim" and the connection of the boost diodes to
the switching nodes gives a nice ~12-13 volt Vdd to common rail above
the lockout threshold for the flying driver's supply nodes and keeps all
the component dissipation low.

https://www.dropbox.com/s/sv5fox0ywcmpypv/Sine.PNG?dl=0

Total miserable nightmare to get working right as a prototype, losing
gate drivers for unknown reason, these chips seem way slower than the
~50n prop delay specified in the datasheet, can't get up to speed. I
don't think this 4120 likes being driven the way it's connected here in
reality and they're dying on me, or I've made an error in the
implementation somewhere i can't readily spot.

Anyway, I hate it, looking for any suggestions or alternate gate-drive
schemes for this, I'd like a cheaper faster and more rugged one, as
someone mentioned I don't really need the ADuM4120's internal
transformer isolation if I could find a good way to level-shift the
incoming logic level drive appropriately to the negative rails the lower
FETs have. Thanks

I can envision a lot of DC circulating in addition to switching
losses.

I think the flying-diode connection to the opposing switching nodes
helps there with negative feedback. If one side develops a DC-offset the
boost gate-drive voltage on the opposing side increases or decreases to
push it back


Or add a capacitor!

Where, in line with the Ls?


John Larkin
Guest

Fri May 01, 2020 10:45 pm   



On Fri, 1 May 2020 16:44:29 -0400, bitrex <user_at_example.net> wrote:

Quote:
On 5/1/2020 4:41 PM, bitrex wrote:
On 5/1/2020 4:21 PM, John Larkin wrote:
On Fri, 1 May 2020 15:45:45 -0400, bitrex <user_at_example.net> wrote:

On 5/1/2020 3:40 PM, John Larkin wrote:
On Fri, 1 May 2020 15:17:11 -0400, bitrex <user_at_example.net> wrote:

On 5/1/2020 2:47 PM, John Larkin wrote:
On Fri, 1 May 2020 14:03:15 -0400, bitrex <user_at_example.net> wrote:

Here's the situation in simplified schematic form, generate a
high-efficiency sine wave at around 3-5MHz putting out about 5 watts
into resistive load:

https://www.dropbox.com/s/tz1zp0d8oy8zkws/IMG_20200501_133832793.jpg?dl=0


Just drive it like two half-bridges with appropriate logic-level
wavaeforms (some dead-time) and if you look at the two switching
nodes
together on a plot you get the red/black waveform there under
inductor
L1. LC filter it through a coupled inductor. and Bob's your Dad's
uncle.
in theory.

First attempt at it on a protoboard:

https://www.dropbox.com/s/1n69o0yzhd2rbpk/Schem.PNG?dl=0

"it looks great in the sim" and the connection of the boost
diodes to
the switching nodes gives a nice ~12-13 volt Vdd to common rail
above
the lockout threshold for the flying driver's supply nodes and
keeps all
the component dissipation low.

https://www.dropbox.com/s/sv5fox0ywcmpypv/Sine.PNG?dl=0

Total miserable nightmare to get working right as a prototype,
losing
gate drivers for unknown reason, these chips seem way slower than
the
~50n prop delay specified in the datasheet, can't get up to speed. I
don't think this 4120 likes being driven the way it's connected
here in
reality and they're dying on me, or I've made an error in the
implementation somewhere i can't readily spot.

Anyway, I hate it, looking for any suggestions or alternate
gate-drive
schemes for this, I'd like a cheaper faster and more rugged one, as
someone mentioned I don't really need the ADuM4120's internal
transformer isolation if I could find a good way to level-shift the
incoming logic level drive appropriately to the negative rails
the lower
FETs have. Thanks

I can envision a lot of DC circulating in addition to switching
losses.

I think the flying-diode connection to the opposing switching nodes
helps there with negative feedback. If one side develops a
DC-offset the
boost gate-drive voltage on the opposing side increases or
decreases to
push it back


Or add a capacitor!

Where, in line with the Ls?

Yes.

Even a small duty cycle mismatch could pump a lot of DC current
through those inductors.


I'll check if that stops it trashing gate drivers at least, the output
stage can handle a bit of offset but it does look like the more fragile
gate-driver FETs are going to be unhappy with that. They're
thermally-limited but it probably can't react fast enough to big
offset-related spikes. :(

The AD devices and FETs are too well-matched in the sim and as such the
DC-problem doesn't obviously rear up.


We have a zillion of the IXYS drivers in stock. I could send you some.
It's a Zen thing, the best way to design is not to design.

--

John Larkin Highland Technology, Inc
picosecond timing precision measurement

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

bitrex
Guest

Fri May 01, 2020 10:45 pm   



On 5/1/2020 4:51 PM, John Larkin wrote:
Quote:
On Fri, 1 May 2020 16:44:29 -0400, bitrex <user_at_example.net> wrote:

On 5/1/2020 4:41 PM, bitrex wrote:
On 5/1/2020 4:21 PM, John Larkin wrote:
On Fri, 1 May 2020 15:45:45 -0400, bitrex <user_at_example.net> wrote:

On 5/1/2020 3:40 PM, John Larkin wrote:
On Fri, 1 May 2020 15:17:11 -0400, bitrex <user_at_example.net> wrote:

On 5/1/2020 2:47 PM, John Larkin wrote:
On Fri, 1 May 2020 14:03:15 -0400, bitrex <user_at_example.net> wrote:

Here's the situation in simplified schematic form, generate a
high-efficiency sine wave at around 3-5MHz putting out about 5 watts
into resistive load:

https://www.dropbox.com/s/tz1zp0d8oy8zkws/IMG_20200501_133832793.jpg?dl=0


Just drive it like two half-bridges with appropriate logic-level
wavaeforms (some dead-time) and if you look at the two switching
nodes
together on a plot you get the red/black waveform there under
inductor
L1. LC filter it through a coupled inductor. and Bob's your Dad's
uncle.
in theory.

First attempt at it on a protoboard:

https://www.dropbox.com/s/1n69o0yzhd2rbpk/Schem.PNG?dl=0

"it looks great in the sim" and the connection of the boost
diodes to
the switching nodes gives a nice ~12-13 volt Vdd to common rail
above
the lockout threshold for the flying driver's supply nodes and
keeps all
the component dissipation low.

https://www.dropbox.com/s/sv5fox0ywcmpypv/Sine.PNG?dl=0

Total miserable nightmare to get working right as a prototype,
losing
gate drivers for unknown reason, these chips seem way slower than
the
~50n prop delay specified in the datasheet, can't get up to speed. I
don't think this 4120 likes being driven the way it's connected
here in
reality and they're dying on me, or I've made an error in the
implementation somewhere i can't readily spot.

Anyway, I hate it, looking for any suggestions or alternate
gate-drive
schemes for this, I'd like a cheaper faster and more rugged one, as
someone mentioned I don't really need the ADuM4120's internal
transformer isolation if I could find a good way to level-shift the
incoming logic level drive appropriately to the negative rails
the lower
FETs have. Thanks

I can envision a lot of DC circulating in addition to switching
losses.

I think the flying-diode connection to the opposing switching nodes
helps there with negative feedback. If one side develops a
DC-offset the
boost gate-drive voltage on the opposing side increases or
decreases to
push it back


Or add a capacitor!

Where, in line with the Ls?

Yes.

Even a small duty cycle mismatch could pump a lot of DC current
through those inductors.


I'll check if that stops it trashing gate drivers at least, the output
stage can handle a bit of offset but it does look like the more fragile
gate-driver FETs are going to be unhappy with that. They're
thermally-limited but it probably can't react fast enough to big
offset-related spikes. :(

The AD devices and FETs are too well-matched in the sim and as such the
DC-problem doesn't obviously rear up.

We have a zillion of the IXYS drivers in stock. I could send you some.
It's a Zen thing, the best way to design is not to design.


Thanks! but i don't see how to make it work in this configuration look
like they have a common ground between sections.

That ADuM-BS is nice in theory because they take logic level on one side
and HV on the other, don't have to think too hard about level-shifting
the drive from the uP or whatever.

bitrex
Guest

Fri May 01, 2020 11:45 pm   



On 5/1/2020 4:51 PM, John Larkin wrote:
Quote:
On Fri, 1 May 2020 16:44:29 -0400, bitrex <user_at_example.net> wrote:

On 5/1/2020 4:41 PM, bitrex wrote:
On 5/1/2020 4:21 PM, John Larkin wrote:
On Fri, 1 May 2020 15:45:45 -0400, bitrex <user_at_example.net> wrote:

On 5/1/2020 3:40 PM, John Larkin wrote:
On Fri, 1 May 2020 15:17:11 -0400, bitrex <user_at_example.net> wrote:

On 5/1/2020 2:47 PM, John Larkin wrote:
On Fri, 1 May 2020 14:03:15 -0400, bitrex <user_at_example.net> wrote:

Here's the situation in simplified schematic form, generate a
high-efficiency sine wave at around 3-5MHz putting out about 5 watts
into resistive load:

https://www.dropbox.com/s/tz1zp0d8oy8zkws/IMG_20200501_133832793.jpg?dl=0


Just drive it like two half-bridges with appropriate logic-level
wavaeforms (some dead-time) and if you look at the two switching
nodes
together on a plot you get the red/black waveform there under
inductor
L1. LC filter it through a coupled inductor. and Bob's your Dad's
uncle.
in theory.

First attempt at it on a protoboard:

https://www.dropbox.com/s/1n69o0yzhd2rbpk/Schem.PNG?dl=0

"it looks great in the sim" and the connection of the boost
diodes to
the switching nodes gives a nice ~12-13 volt Vdd to common rail
above
the lockout threshold for the flying driver's supply nodes and
keeps all
the component dissipation low.

https://www.dropbox.com/s/sv5fox0ywcmpypv/Sine.PNG?dl=0

Total miserable nightmare to get working right as a prototype,
losing
gate drivers for unknown reason, these chips seem way slower than
the
~50n prop delay specified in the datasheet, can't get up to speed. I
don't think this 4120 likes being driven the way it's connected
here in
reality and they're dying on me, or I've made an error in the
implementation somewhere i can't readily spot.

Anyway, I hate it, looking for any suggestions or alternate
gate-drive
schemes for this, I'd like a cheaper faster and more rugged one, as
someone mentioned I don't really need the ADuM4120's internal
transformer isolation if I could find a good way to level-shift the
incoming logic level drive appropriately to the negative rails
the lower
FETs have. Thanks

I can envision a lot of DC circulating in addition to switching
losses.

I think the flying-diode connection to the opposing switching nodes
helps there with negative feedback. If one side develops a
DC-offset the
boost gate-drive voltage on the opposing side increases or
decreases to
push it back


Or add a capacitor!

Where, in line with the Ls?

Yes.

Even a small duty cycle mismatch could pump a lot of DC current
through those inductors.


I'll check if that stops it trashing gate drivers at least, the output
stage can handle a bit of offset but it does look like the more fragile
gate-driver FETs are going to be unhappy with that. They're
thermally-limited but it probably can't react fast enough to big
offset-related spikes. :(

The AD devices and FETs are too well-matched in the sim and as such the
DC-problem doesn't obviously rear up.

We have a zillion of the IXYS drivers in stock. I could send you some.
It's a Zen thing, the best way to design is not to design.


At ~5 watts into a load with the blocking caps in place and rails as
shown in the sim at least the efficiency of this structure is ~90%

John Larkin
Guest

Fri May 01, 2020 11:45 pm   



On Fri, 1 May 2020 17:39:10 -0400, bitrex <user_at_example.net> wrote:

Quote:
On 5/1/2020 4:51 PM, John Larkin wrote:
On Fri, 1 May 2020 16:44:29 -0400, bitrex <user_at_example.net> wrote:

On 5/1/2020 4:41 PM, bitrex wrote:
On 5/1/2020 4:21 PM, John Larkin wrote:
On Fri, 1 May 2020 15:45:45 -0400, bitrex <user_at_example.net> wrote:

On 5/1/2020 3:40 PM, John Larkin wrote:
On Fri, 1 May 2020 15:17:11 -0400, bitrex <user_at_example.net> wrote:

On 5/1/2020 2:47 PM, John Larkin wrote:
On Fri, 1 May 2020 14:03:15 -0400, bitrex <user_at_example.net> wrote:

Here's the situation in simplified schematic form, generate a
high-efficiency sine wave at around 3-5MHz putting out about 5 watts
into resistive load:

https://www.dropbox.com/s/tz1zp0d8oy8zkws/IMG_20200501_133832793.jpg?dl=0


Just drive it like two half-bridges with appropriate logic-level
wavaeforms (some dead-time) and if you look at the two switching
nodes
together on a plot you get the red/black waveform there under
inductor
L1. LC filter it through a coupled inductor. and Bob's your Dad's
uncle.
in theory.

First attempt at it on a protoboard:

https://www.dropbox.com/s/1n69o0yzhd2rbpk/Schem.PNG?dl=0

"it looks great in the sim" and the connection of the boost
diodes to
the switching nodes gives a nice ~12-13 volt Vdd to common rail
above
the lockout threshold for the flying driver's supply nodes and
keeps all
the component dissipation low.

https://www.dropbox.com/s/sv5fox0ywcmpypv/Sine.PNG?dl=0

Total miserable nightmare to get working right as a prototype,
losing
gate drivers for unknown reason, these chips seem way slower than
the
~50n prop delay specified in the datasheet, can't get up to speed. I
don't think this 4120 likes being driven the way it's connected
here in
reality and they're dying on me, or I've made an error in the
implementation somewhere i can't readily spot.

Anyway, I hate it, looking for any suggestions or alternate
gate-drive
schemes for this, I'd like a cheaper faster and more rugged one, as
someone mentioned I don't really need the ADuM4120's internal
transformer isolation if I could find a good way to level-shift the
incoming logic level drive appropriately to the negative rails
the lower
FETs have. Thanks

I can envision a lot of DC circulating in addition to switching
losses.

I think the flying-diode connection to the opposing switching nodes
helps there with negative feedback. If one side develops a
DC-offset the
boost gate-drive voltage on the opposing side increases or
decreases to
push it back


Or add a capacitor!

Where, in line with the Ls?

Yes.

Even a small duty cycle mismatch could pump a lot of DC current
through those inductors.


I'll check if that stops it trashing gate drivers at least, the output
stage can handle a bit of offset but it does look like the more fragile
gate-driver FETs are going to be unhappy with that. They're
thermally-limited but it probably can't react fast enough to big
offset-related spikes. :(

The AD devices and FETs are too well-matched in the sim and as such the
DC-problem doesn't obviously rear up.

We have a zillion of the IXYS drivers in stock. I could send you some.
It's a Zen thing, the best way to design is not to design.


Thanks! but i don't see how to make it work in this configuration look
like they have a common ground between sections.

That ADuM-BS is nice in theory because they take logic level on one side
and HV on the other, don't have to think too hard about level-shifting
the drive from the uP or whatever.


I meant to use them as the power output stages, not as gate drivers.

--

John Larkin Highland Technology, Inc
picosecond timing precision measurement

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

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