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bitrex
Guest

Sat May 02, 2020 12:45 am   



On 5/1/2020 6:28 PM, John Larkin wrote:
Quote:
On Fri, 1 May 2020 17:39:10 -0400, bitrex <user_at_example.net> wrote:

On 5/1/2020 4:51 PM, John Larkin wrote:
On Fri, 1 May 2020 16:44:29 -0400, bitrex <user_at_example.net> wrote:

On 5/1/2020 4:41 PM, bitrex wrote:
On 5/1/2020 4:21 PM, John Larkin wrote:
On Fri, 1 May 2020 15:45:45 -0400, bitrex <user_at_example.net> wrote:

On 5/1/2020 3:40 PM, John Larkin wrote:
On Fri, 1 May 2020 15:17:11 -0400, bitrex <user_at_example.net> wrote:

On 5/1/2020 2:47 PM, John Larkin wrote:
On Fri, 1 May 2020 14:03:15 -0400, bitrex <user_at_example.net> wrote:

Here's the situation in simplified schematic form, generate a
high-efficiency sine wave at around 3-5MHz putting out about 5 watts
into resistive load:

https://www.dropbox.com/s/tz1zp0d8oy8zkws/IMG_20200501_133832793.jpg?dl=0


Just drive it like two half-bridges with appropriate logic-level
wavaeforms (some dead-time) and if you look at the two switching
nodes
together on a plot you get the red/black waveform there under
inductor
L1. LC filter it through a coupled inductor. and Bob's your Dad's
uncle.
in theory.

First attempt at it on a protoboard:

https://www.dropbox.com/s/1n69o0yzhd2rbpk/Schem.PNG?dl=0

"it looks great in the sim" and the connection of the boost
diodes to
the switching nodes gives a nice ~12-13 volt Vdd to common rail
above
the lockout threshold for the flying driver's supply nodes and
keeps all
the component dissipation low.

https://www.dropbox.com/s/sv5fox0ywcmpypv/Sine.PNG?dl=0

Total miserable nightmare to get working right as a prototype,
losing
gate drivers for unknown reason, these chips seem way slower than
the
~50n prop delay specified in the datasheet, can't get up to speed. I
don't think this 4120 likes being driven the way it's connected
here in
reality and they're dying on me, or I've made an error in the
implementation somewhere i can't readily spot.

Anyway, I hate it, looking for any suggestions or alternate
gate-drive
schemes for this, I'd like a cheaper faster and more rugged one, as
someone mentioned I don't really need the ADuM4120's internal
transformer isolation if I could find a good way to level-shift the
incoming logic level drive appropriately to the negative rails
the lower
FETs have. Thanks

I can envision a lot of DC circulating in addition to switching
losses.

I think the flying-diode connection to the opposing switching nodes
helps there with negative feedback. If one side develops a
DC-offset the
boost gate-drive voltage on the opposing side increases or
decreases to
push it back


Or add a capacitor!

Where, in line with the Ls?

Yes.

Even a small duty cycle mismatch could pump a lot of DC current
through those inductors.


I'll check if that stops it trashing gate drivers at least, the output
stage can handle a bit of offset but it does look like the more fragile
gate-driver FETs are going to be unhappy with that. They're
thermally-limited but it probably can't react fast enough to big
offset-related spikes. :(

The AD devices and FETs are too well-matched in the sim and as such the
DC-problem doesn't obviously rear up.

We have a zillion of the IXYS drivers in stock. I could send you some.
It's a Zen thing, the best way to design is not to design.


Thanks! but i don't see how to make it work in this configuration look
like they have a common ground between sections.

That ADuM-BS is nice in theory because they take logic level on one side
and HV on the other, don't have to think too hard about level-shifting
the drive from the uP or whatever.

I meant to use them as the power output stages, not as gate drivers.


I understand, but still looks like a problem. there's two complimentary
pairs in the same package but the input ground and the grounds of both
low-side FETs are common.

piglet
Guest

Sat May 02, 2020 11:45 am   



On 01/05/2020 8:08 pm, bitrex wrote:
Quote:
On 5/1/2020 2:47 PM, John Larkin wrote:
On Fri, 1 May 2020 14:03:15 -0400, bitrex <user_at_example.net> wrote:

Here's the situation in simplified schematic form, generate a
high-efficiency sine wave at around 3-5MHz putting out about 5 watts
into resistive load:

https://www.dropbox.com/s/tz1zp0d8oy8zkws/IMG_20200501_133832793.jpg?dl=0


Just drive it like two half-bridges with appropriate logic-level
wavaeforms (some dead-time) and if you look at the two switching nodes
together on a plot you get the red/black waveform there under inductor
L1. LC filter it through a coupled inductor. and Bob's your Dad's uncle.
in theory.

First attempt at it on a protoboard:

https://www.dropbox.com/s/1n69o0yzhd2rbpk/Schem.PNG?dl=0

"it looks great in the sim" and the connection of the boost diodes to
the switching nodes gives a nice ~12-13 volt Vdd to common rail above
the lockout threshold for the flying driver's supply nodes and keeps all
the component dissipation low.

https://www.dropbox.com/s/sv5fox0ywcmpypv/Sine.PNG?dl=0

Total miserable nightmare to get working right as a prototype, losing
gate drivers for unknown reason, these chips seem way slower than the
~50n prop delay specified in the datasheet, can't get up to speed. I
don't think this 4120 likes being driven the way it's connected here in
reality and they're dying on me, or I've made an error in the
implementation somewhere i can't readily spot.

Anyway, I hate it, looking for any suggestions or alternate gate-drive
schemes for this, I'd like a cheaper faster and more rugged one, as
someone mentioned I don't really need the ADuM4120's internal
transformer isolation if I could find a good way to level-shift the
incoming logic level drive appropriately to the negative rails the lower
FETs have. Thanks

I can envision a lot of DC circulating in addition to switching
losses.

This will be difficult with mosfets and regular gate drivers, as you
note. You might consider something simpler, like a single mosfet or
SiC fet in a tuned class-C amp. RF stuff. One power part on a heat
sink.

You could probably use some gate drivers, like IXDN602, as the output
device itself if all you need is 5 watts. They are cheap and fast and
handy for a lot more than gate driving.


Huh. That's an interesting chip. Goes up to 35 input, too. Wonder if
they'd like being paralleled...

This is my second idea for KISS-approach:

https://www.dropbox.com/s/dewy6eqpggoagg5/IMG_20200501_145539343.jpg?dl=0

Use two non-isolated gate driver chips with like 10ns propagation delay.
One of two shown. Keep the flying-boostrap connection the same. And
"level shift" simply by capactively coupling the logic inputs.

It needs an extra two regulators to make a Vcc appropriately above the
negative supplies on the primary side. But I think it's better than
messing with four isolated drivers, I don't really need them for
isolation just level-shifting.


Why do you need the funny voltage power rails? If you're making a sine
wave let your output LC do the voltage transformation. Sounds like
you're trying to make a sort of 80meter ham band QRP transmitter but
using an SMPSU approach?

Did you rule out traditional push-pull (two low side n-ch devices) for
some reason?

piglet

bitrex
Guest

Sat May 02, 2020 6:45 pm   



On 5/2/2020 5:59 AM, piglet wrote:
Quote:
On 01/05/2020 8:08 pm, bitrex wrote:
On 5/1/2020 2:47 PM, John Larkin wrote:
On Fri, 1 May 2020 14:03:15 -0400, bitrex <user_at_example.net> wrote:

Here's the situation in simplified schematic form, generate a
high-efficiency sine wave at around 3-5MHz putting out about 5 watts
into resistive load:

https://www.dropbox.com/s/tz1zp0d8oy8zkws/IMG_20200501_133832793.jpg?dl=0


Just drive it like two half-bridges with appropriate logic-level
wavaeforms (some dead-time) and if you look at the two switching nodes
together on a plot you get the red/black waveform there under inductor
L1. LC filter it through a coupled inductor. and Bob's your Dad's
uncle.
in theory.

First attempt at it on a protoboard:

https://www.dropbox.com/s/1n69o0yzhd2rbpk/Schem.PNG?dl=0

"it looks great in the sim" and the connection of the boost diodes to
the switching nodes gives a nice ~12-13 volt Vdd to common rail above
the lockout threshold for the flying driver's supply nodes and keeps
all
the component dissipation low.

https://www.dropbox.com/s/sv5fox0ywcmpypv/Sine.PNG?dl=0

Total miserable nightmare to get working right as a prototype, losing
gate drivers for unknown reason, these chips seem way slower than the
~50n prop delay specified in the datasheet, can't get up to speed. I
don't think this 4120 likes being driven the way it's connected here in
reality and they're dying on me, or I've made an error in the
implementation somewhere i can't readily spot.

Anyway, I hate it, looking for any suggestions or alternate gate-drive
schemes for this, I'd like a cheaper faster and more rugged one, as
someone mentioned I don't really need the ADuM4120's internal
transformer isolation if I could find a good way to level-shift the
incoming logic level drive appropriately to the negative rails the
lower
FETs have. Thanks

I can envision a lot of DC circulating in addition to switching
losses.

This will be difficult with mosfets and regular gate drivers, as you
note. You might consider something simpler, like a single mosfet or
SiC fet in a tuned class-C amp. RF stuff. One power part on a heat
sink.

You could probably use some gate drivers, like IXDN602, as the output
device itself if all you need is 5 watts. They are cheap and fast and
handy for a lot more than gate driving.


Huh. That's an interesting chip. Goes up to 35 input, too. Wonder if
they'd like being paralleled...

This is my second idea for KISS-approach:

https://www.dropbox.com/s/dewy6eqpggoagg5/IMG_20200501_145539343.jpg?dl=0


Use two non-isolated gate driver chips with like 10ns propagation
delay. One of two shown. Keep the flying-boostrap connection the same.
And "level shift" simply by capactively coupling the logic inputs.

It needs an extra two regulators to make a Vcc appropriately above the
negative supplies on the primary side. But I think it's better than
messing with four isolated drivers, I don't really need them for
isolation just level-shifting.

Why do you need the funny voltage power rails? If you're making a sine
wave let your output LC do the voltage transformation. Sounds like
you're trying to make a sort of 80meter ham band QRP transmitter but
using an SMPSU approach?

Did you rule out traditional push-pull (two low side n-ch devices) for
some reason?

piglet


Like using a center-tapped transformer, you mean?


Guest

Sat May 02, 2020 7:45 pm   



On Sat, 2 May 2020 13:05:54 -0400, bitrex <user_at_example.net> wrote:

Quote:
On 5/2/2020 5:59 AM, piglet wrote:
On 01/05/2020 8:08 pm, bitrex wrote:
On 5/1/2020 2:47 PM, John Larkin wrote:
On Fri, 1 May 2020 14:03:15 -0400, bitrex <user_at_example.net> wrote:

Here's the situation in simplified schematic form, generate a
high-efficiency sine wave at around 3-5MHz putting out about 5 watts
into resistive load:

https://www.dropbox.com/s/tz1zp0d8oy8zkws/IMG_20200501_133832793.jpg?dl=0


Just drive it like two half-bridges with appropriate logic-level
wavaeforms (some dead-time) and if you look at the two switching nodes
together on a plot you get the red/black waveform there under inductor
L1. LC filter it through a coupled inductor. and Bob's your Dad's
uncle.
in theory.

First attempt at it on a protoboard:

https://www.dropbox.com/s/1n69o0yzhd2rbpk/Schem.PNG?dl=0

"it looks great in the sim" and the connection of the boost diodes to
the switching nodes gives a nice ~12-13 volt Vdd to common rail above
the lockout threshold for the flying driver's supply nodes and keeps
all
the component dissipation low.

https://www.dropbox.com/s/sv5fox0ywcmpypv/Sine.PNG?dl=0

Total miserable nightmare to get working right as a prototype, losing
gate drivers for unknown reason, these chips seem way slower than the
~50n prop delay specified in the datasheet, can't get up to speed. I
don't think this 4120 likes being driven the way it's connected here in
reality and they're dying on me, or I've made an error in the
implementation somewhere i can't readily spot.

Anyway, I hate it, looking for any suggestions or alternate gate-drive
schemes for this, I'd like a cheaper faster and more rugged one, as
someone mentioned I don't really need the ADuM4120's internal
transformer isolation if I could find a good way to level-shift the
incoming logic level drive appropriately to the negative rails the
lower
FETs have. Thanks

I can envision a lot of DC circulating in addition to switching
losses.

This will be difficult with mosfets and regular gate drivers, as you
note. You might consider something simpler, like a single mosfet or
SiC fet in a tuned class-C amp. RF stuff. One power part on a heat
sink.

You could probably use some gate drivers, like IXDN602, as the output
device itself if all you need is 5 watts. They are cheap and fast and
handy for a lot more than gate driving.


Huh. That's an interesting chip. Goes up to 35 input, too. Wonder if
they'd like being paralleled...

This is my second idea for KISS-approach:

https://www.dropbox.com/s/dewy6eqpggoagg5/IMG_20200501_145539343.jpg?dl=0


Use two non-isolated gate driver chips with like 10ns propagation
delay. One of two shown. Keep the flying-boostrap connection the same.
And "level shift" simply by capactively coupling the logic inputs.

It needs an extra two regulators to make a Vcc appropriately above the
negative supplies on the primary side. But I think it's better than
messing with four isolated drivers, I don't really need them for
isolation just level-shifting.

Why do you need the funny voltage power rails? If you're making a sine
wave let your output LC do the voltage transformation. Sounds like
you're trying to make a sort of 80meter ham band QRP transmitter but
using an SMPSU approach?

Did you rule out traditional push-pull (two low side n-ch devices) for
some reason?

piglet


Like using a center-tapped transformer, you mean?


Or at least a single positive supply.

If you are going to use discrete fets, it's easy to drive them if the
sources are all ground.

Sloman will be happy to design a transformer for you.



--

John Larkin Highland Technology, Inc

Science teaches us to doubt.

Claude Bernard

piglet
Guest

Sat May 02, 2020 7:45 pm   



On 02/05/2020 6:05 pm, bitrex wrote:
Quote:
On 5/2/2020 5:59 AM, piglet wrote:
On 01/05/2020 8:08 pm, bitrex wrote:
On 5/1/2020 2:47 PM, John Larkin wrote:
On Fri, 1 May 2020 14:03:15 -0400, bitrex <user_at_example.net> wrote:

Here's the situation in simplified schematic form, generate a
high-efficiency sine wave at around 3-5MHz putting out about 5 watts
into resistive load:

https://www.dropbox.com/s/tz1zp0d8oy8zkws/IMG_20200501_133832793.jpg?dl=0


Just drive it like two half-bridges with appropriate logic-level
wavaeforms (some dead-time) and if you look at the two switching nodes
together on a plot you get the red/black waveform there under inductor
L1. LC filter it through a coupled inductor. and Bob's your Dad's
uncle.
in theory.

First attempt at it on a protoboard:

https://www.dropbox.com/s/1n69o0yzhd2rbpk/Schem.PNG?dl=0

"it looks great in the sim" and the connection of the boost diodes to
the switching nodes gives a nice ~12-13 volt Vdd to common rail above
the lockout threshold for the flying driver's supply nodes and
keeps all
the component dissipation low.

https://www.dropbox.com/s/sv5fox0ywcmpypv/Sine.PNG?dl=0

Total miserable nightmare to get working right as a prototype, losing
gate drivers for unknown reason, these chips seem way slower than the
~50n prop delay specified in the datasheet, can't get up to speed. I
don't think this 4120 likes being driven the way it's connected
here in
reality and they're dying on me, or I've made an error in the
implementation somewhere i can't readily spot.

Anyway, I hate it, looking for any suggestions or alternate gate-drive
schemes for this, I'd like a cheaper faster and more rugged one, as
someone mentioned I don't really need the ADuM4120's internal
transformer isolation if I could find a good way to level-shift the
incoming logic level drive appropriately to the negative rails the
lower
FETs have. Thanks

I can envision a lot of DC circulating in addition to switching
losses.

This will be difficult with mosfets and regular gate drivers, as you
note. You might consider something simpler, like a single mosfet or
SiC fet in a tuned class-C amp. RF stuff. One power part on a heat
sink.

You could probably use some gate drivers, like IXDN602, as the output
device itself if all you need is 5 watts. They are cheap and fast and
handy for a lot more than gate driving.


Huh. That's an interesting chip. Goes up to 35 input, too. Wonder if
they'd like being paralleled...

This is my second idea for KISS-approach:

https://www.dropbox.com/s/dewy6eqpggoagg5/IMG_20200501_145539343.jpg?dl=0


Use two non-isolated gate driver chips with like 10ns propagation
delay. One of two shown. Keep the flying-boostrap connection the
same. And "level shift" simply by capactively coupling the logic inputs.

It needs an extra two regulators to make a Vcc appropriately above
the negative supplies on the primary side. But I think it's better
than messing with four isolated drivers, I don't really need them for
isolation just level-shifting.

Why do you need the funny voltage power rails? If you're making a sine
wave let your output LC do the voltage transformation. Sounds like
you're trying to make a sort of 80meter ham band QRP transmitter but
using an SMPSU approach?

Did you rule out traditional push-pull (two low side n-ch devices) for
some reason?

piglet


Like using a center-tapped transformer, you mean?


Yep, but you might find off-the-shelf dual inductors or versa-pac
thingies that fit the bill.

piglet

bitrex
Guest

Sat May 02, 2020 7:45 pm   



On 5/2/2020 1:56 PM, jlarkin_at_highlandsniptechnology.com wrote:
Quote:
On Sat, 2 May 2020 13:05:54 -0400, bitrex <user_at_example.net> wrote:

On 5/2/2020 5:59 AM, piglet wrote:
On 01/05/2020 8:08 pm, bitrex wrote:
On 5/1/2020 2:47 PM, John Larkin wrote:
On Fri, 1 May 2020 14:03:15 -0400, bitrex <user_at_example.net> wrote:

Here's the situation in simplified schematic form, generate a
high-efficiency sine wave at around 3-5MHz putting out about 5 watts
into resistive load:

https://www.dropbox.com/s/tz1zp0d8oy8zkws/IMG_20200501_133832793.jpg?dl=0


Just drive it like two half-bridges with appropriate logic-level
wavaeforms (some dead-time) and if you look at the two switching nodes
together on a plot you get the red/black waveform there under inductor
L1. LC filter it through a coupled inductor. and Bob's your Dad's
uncle.
in theory.

First attempt at it on a protoboard:

https://www.dropbox.com/s/1n69o0yzhd2rbpk/Schem.PNG?dl=0

"it looks great in the sim" and the connection of the boost diodes to
the switching nodes gives a nice ~12-13 volt Vdd to common rail above
the lockout threshold for the flying driver's supply nodes and keeps
all
the component dissipation low.

https://www.dropbox.com/s/sv5fox0ywcmpypv/Sine.PNG?dl=0

Total miserable nightmare to get working right as a prototype, losing
gate drivers for unknown reason, these chips seem way slower than the
~50n prop delay specified in the datasheet, can't get up to speed. I
don't think this 4120 likes being driven the way it's connected here in
reality and they're dying on me, or I've made an error in the
implementation somewhere i can't readily spot.

Anyway, I hate it, looking for any suggestions or alternate gate-drive
schemes for this, I'd like a cheaper faster and more rugged one, as
someone mentioned I don't really need the ADuM4120's internal
transformer isolation if I could find a good way to level-shift the
incoming logic level drive appropriately to the negative rails the
lower
FETs have. Thanks

I can envision a lot of DC circulating in addition to switching
losses.

This will be difficult with mosfets and regular gate drivers, as you
note. You might consider something simpler, like a single mosfet or
SiC fet in a tuned class-C amp. RF stuff. One power part on a heat
sink.

You could probably use some gate drivers, like IXDN602, as the output
device itself if all you need is 5 watts. They are cheap and fast and
handy for a lot more than gate driving.


Huh. That's an interesting chip. Goes up to 35 input, too. Wonder if
they'd like being paralleled...

This is my second idea for KISS-approach:

https://www.dropbox.com/s/dewy6eqpggoagg5/IMG_20200501_145539343.jpg?dl=0


Use two non-isolated gate driver chips with like 10ns propagation
delay. One of two shown. Keep the flying-boostrap connection the same.
And "level shift" simply by capactively coupling the logic inputs.

It needs an extra two regulators to make a Vcc appropriately above the
negative supplies on the primary side. But I think it's better than
messing with four isolated drivers, I don't really need them for
isolation just level-shifting.

Why do you need the funny voltage power rails? If you're making a sine
wave let your output LC do the voltage transformation. Sounds like
you're trying to make a sort of 80meter ham band QRP transmitter but
using an SMPSU approach?

Did you rule out traditional push-pull (two low side n-ch devices) for
some reason?

piglet


Like using a center-tapped transformer, you mean?

Or at least a single positive supply.

If you are going to use discrete fets, it's easy to drive them if the
sources are all ground.


I agree, these negative rails are a pain. My alternative idea is to do
something like this, four FETs and one phase of this:

<https://www.researchgate.net/profile/Yu_Zhang368/publication/224633035/figure/fig1/AS:386501029449729_at_1469160434606/Three-phase-full-bridge-inverters.png>

I could keep the +25 and 25/2 rails for the top two FETs, and keep the
drive logic the same as I have it I think. Use an off the shelf L and
l:l transformer. The client would like to be able to raise and lower the
output voltage in steps by adjusting the supply voltages in
steps...maybe set a step-up ratio to the midpoint of the desired range,
actually. 50-200V P2P


Quote:
Sloman will be happy to design a transformer for you.


He likes that circuit very much.


Guest

Sat May 02, 2020 8:45 pm   



On Fri, 1 May 2020 14:03:15 -0400, bitrex <user_at_example.net> wrote:

Quote:
Here's the situation in simplified schematic form, generate a
high-efficiency sine wave at around 3-5MHz putting out about 5 watts
into resistive load:

https://www.dropbox.com/s/tz1zp0d8oy8zkws/IMG_20200501_133832793.jpg?dl=0

Just drive it like two half-bridges with appropriate logic-level
wavaeforms (some dead-time) and if you look at the two switching nodes
together on a plot you get the red/black waveform there under inductor
L1. LC filter it through a coupled inductor. and Bob's your Dad's uncle.
in theory.

First attempt at it on a protoboard:

https://www.dropbox.com/s/1n69o0yzhd2rbpk/Schem.PNG?dl=0

"it looks great in the sim" and the connection of the boost diodes to
the switching nodes gives a nice ~12-13 volt Vdd to common rail above
the lockout threshold for the flying driver's supply nodes and keeps all
the component dissipation low.

https://www.dropbox.com/s/sv5fox0ywcmpypv/Sine.PNG?dl=0

Total miserable nightmare to get working right as a prototype, losing
gate drivers for unknown reason, these chips seem way slower than the
~50n prop delay specified in the datasheet, can't get up to speed. I
don't think this 4120 likes being driven the way it's connected here in
reality and they're dying on me, or I've made an error in the
implementation somewhere i can't readily spot.

Anyway, I hate it, looking for any suggestions or alternate gate-drive
schemes for this, I'd like a cheaper faster and more rugged one, as
someone mentioned I don't really need the ADuM4120's internal
transformer isolation if I could find a good way to level-shift the
incoming logic level drive appropriately to the negative rails the lower
FETs have. Thanks


Something like this maybe?

https://www.dropbox.com/s/87fj0uyt8llt6hq/5W_Sine_Waves.JPG?raw=1

If you need more voltage, you could do a Colpitts sort of step-up for
the bandpass case. Takes one more cap.

Aside, I have been burned a couple of times (literally burned) by
selecting inductors that appeared to be within their ratings, but got
hot from core loss and/or skin loss.

That's happening right now on our 300 watt class-D amp. Fortunately,
it wouldn't be awful to hang some toroids on the surface-mount
inductor footprints.





--

John Larkin Highland Technology, Inc

Science teaches us to doubt.

Claude Bernard

bitrex
Guest

Sat May 02, 2020 9:45 pm   



On 5/2/2020 3:07 PM, jlarkin_at_highlandsniptechnology.com wrote:
Quote:
On Fri, 1 May 2020 14:03:15 -0400, bitrex <user_at_example.net> wrote:

Here's the situation in simplified schematic form, generate a
high-efficiency sine wave at around 3-5MHz putting out about 5 watts
into resistive load:

https://www.dropbox.com/s/tz1zp0d8oy8zkws/IMG_20200501_133832793.jpg?dl=0

Just drive it like two half-bridges with appropriate logic-level
wavaeforms (some dead-time) and if you look at the two switching nodes
together on a plot you get the red/black waveform there under inductor
L1. LC filter it through a coupled inductor. and Bob's your Dad's uncle.
in theory.

First attempt at it on a protoboard:

https://www.dropbox.com/s/1n69o0yzhd2rbpk/Schem.PNG?dl=0

"it looks great in the sim" and the connection of the boost diodes to
the switching nodes gives a nice ~12-13 volt Vdd to common rail above
the lockout threshold for the flying driver's supply nodes and keeps all
the component dissipation low.

https://www.dropbox.com/s/sv5fox0ywcmpypv/Sine.PNG?dl=0

Total miserable nightmare to get working right as a prototype, losing
gate drivers for unknown reason, these chips seem way slower than the
~50n prop delay specified in the datasheet, can't get up to speed. I
don't think this 4120 likes being driven the way it's connected here in
reality and they're dying on me, or I've made an error in the
implementation somewhere i can't readily spot.

Anyway, I hate it, looking for any suggestions or alternate gate-drive
schemes for this, I'd like a cheaper faster and more rugged one, as
someone mentioned I don't really need the ADuM4120's internal
transformer isolation if I could find a good way to level-shift the
incoming logic level drive appropriately to the negative rails the lower
FETs have. Thanks

Something like this maybe?

https://www.dropbox.com/s/87fj0uyt8llt6hq/5W_Sine_Waves.JPG?raw=1

If you need more voltage, you could do a Colpitts sort of step-up for
the bandpass case. Takes one more cap.

Aside, I have been burned a couple of times (literally burned) by
selecting inductors that appeared to be within their ratings, but got
hot from core loss and/or skin loss.

That's happening right now on our 300 watt class-D amp. Fortunately,
it wouldn't be awful to hang some toroids on the surface-mount
inductor footprints.



Since I have the four-level drive waveforms available already how about
something like this using the IXYS chip:

<https://www.dropbox.com/s/vdsoeigilgxmbrl/IMG_20200502_161215072.jpg?dl=0>

The schottkeys aren't ideal but for low powers should be OK for now I
think. If they need more power at some point I can figure that out later
with a proper half-bridge drivers and external FETs.

bitrex
Guest

Sat May 02, 2020 9:45 pm   



On 5/2/2020 4:25 PM, bitrex wrote:
Quote:
On 5/2/2020 3:07 PM, jlarkin_at_highlandsniptechnology.com wrote:
On Fri, 1 May 2020 14:03:15 -0400, bitrex <user_at_example.net> wrote:

Here's the situation in simplified schematic form, generate a
high-efficiency sine wave at around 3-5MHz putting out about 5 watts
into resistive load:

https://www.dropbox.com/s/tz1zp0d8oy8zkws/IMG_20200501_133832793.jpg?dl=0


Just drive it like two half-bridges with appropriate logic-level
wavaeforms (some dead-time) and if you look at the two switching nodes
together on a plot you get the red/black waveform there under inductor
L1. LC filter it through a coupled inductor. and Bob's your Dad's uncle.
in theory.

First attempt at it on a protoboard:

https://www.dropbox.com/s/1n69o0yzhd2rbpk/Schem.PNG?dl=0

"it looks great in the sim" and the connection of the boost diodes to
the switching nodes gives a nice ~12-13 volt Vdd to common rail above
the lockout threshold for the flying driver's supply nodes and keeps all
the component dissipation low.

https://www.dropbox.com/s/sv5fox0ywcmpypv/Sine.PNG?dl=0

Total miserable nightmare to get working right as a prototype, losing
gate drivers for unknown reason, these chips seem way slower than the
~50n prop delay specified in the datasheet, can't get up to speed. I
don't think this 4120 likes being driven the way it's connected here in
reality and they're dying on me, or I've made an error in the
implementation somewhere i can't readily spot.

Anyway, I hate it, looking for any suggestions or alternate gate-drive
schemes for this, I'd like a cheaper faster and more rugged one, as
someone mentioned I don't really need the ADuM4120's internal
transformer isolation if I could find a good way to level-shift the
incoming logic level drive appropriately to the negative rails the lower
FETs have. Thanks

Something like this maybe?

https://www.dropbox.com/s/87fj0uyt8llt6hq/5W_Sine_Waves.JPG?raw=1

If you need more voltage, you could do a Colpitts sort of step-up for
the bandpass case. Takes one more cap.

Aside, I have been burned a couple of times (literally burned) by
selecting inductors that appeared to be within their ratings, but got
hot from core loss and/or skin loss.

That's happening right now on our 300 watt class-D amp. Fortunately,
it wouldn't be awful to hang some toroids on the surface-mount
inductor footprints.



Since I have the four-level drive waveforms available already how about
something like this using the IXYS chip:

https://www.dropbox.com/s/vdsoeigilgxmbrl/IMG_20200502_161215072.jpg?dl=0

The schottkeys aren't ideal but for low powers should be OK for now I
think. If they need more power at some point I can figure that out later
with a proper half-bridge drivers and external FETs.


Oops, those should both be 25 volt rails, sorry


Guest

Sat May 02, 2020 10:45 pm   



On Sat, 2 May 2020 16:25:57 -0400, bitrex <user_at_example.net> wrote:

Quote:
On 5/2/2020 3:07 PM, jlarkin_at_highlandsniptechnology.com wrote:
On Fri, 1 May 2020 14:03:15 -0400, bitrex <user_at_example.net> wrote:

Here's the situation in simplified schematic form, generate a
high-efficiency sine wave at around 3-5MHz putting out about 5 watts
into resistive load:

https://www.dropbox.com/s/tz1zp0d8oy8zkws/IMG_20200501_133832793.jpg?dl=0

Just drive it like two half-bridges with appropriate logic-level
wavaeforms (some dead-time) and if you look at the two switching nodes
together on a plot you get the red/black waveform there under inductor
L1. LC filter it through a coupled inductor. and Bob's your Dad's uncle.
in theory.

First attempt at it on a protoboard:

https://www.dropbox.com/s/1n69o0yzhd2rbpk/Schem.PNG?dl=0

"it looks great in the sim" and the connection of the boost diodes to
the switching nodes gives a nice ~12-13 volt Vdd to common rail above
the lockout threshold for the flying driver's supply nodes and keeps all
the component dissipation low.

https://www.dropbox.com/s/sv5fox0ywcmpypv/Sine.PNG?dl=0

Total miserable nightmare to get working right as a prototype, losing
gate drivers for unknown reason, these chips seem way slower than the
~50n prop delay specified in the datasheet, can't get up to speed. I
don't think this 4120 likes being driven the way it's connected here in
reality and they're dying on me, or I've made an error in the
implementation somewhere i can't readily spot.

Anyway, I hate it, looking for any suggestions or alternate gate-drive
schemes for this, I'd like a cheaper faster and more rugged one, as
someone mentioned I don't really need the ADuM4120's internal
transformer isolation if I could find a good way to level-shift the
incoming logic level drive appropriately to the negative rails the lower
FETs have. Thanks

Something like this maybe?

https://www.dropbox.com/s/87fj0uyt8llt6hq/5W_Sine_Waves.JPG?raw=1

If you need more voltage, you could do a Colpitts sort of step-up for
the bandpass case. Takes one more cap.

Aside, I have been burned a couple of times (literally burned) by
selecting inductors that appeared to be within their ratings, but got
hot from core loss and/or skin loss.

That's happening right now on our 300 watt class-D amp. Fortunately,
it wouldn't be awful to hang some toroids on the surface-mount
inductor footprints.



Since I have the four-level drive waveforms available already how about
something like this using the IXYS chip:

https://www.dropbox.com/s/vdsoeigilgxmbrl/IMG_20200502_161215072.jpg?dl=0

The schottkeys aren't ideal but for low powers should be OK for now I
think. If they need more power at some point I can figure that out later
with a proper half-bridge drivers and external FETs.


Seems awfully complex to make a sine wave.

The IXYS part claims anti-shoot-thru features, but it might get hot at
high supply voltage and high clock rate. 5 MHz and, say, 25 volts
might not work.

Do you want 100V p-p sine at 5 MHz? Sounds like RF to me. Class C amp
maybe. 50 volt supply, one fet, LC tank.



--

John Larkin Highland Technology, Inc

Science teaches us to doubt.

Claude Bernard

Lasse Langwadt Christense
Guest

Sat May 02, 2020 11:45 pm   



lørdag den 2. maj 2020 kl. 22.46.01 UTC+2 skrev jla...@highlandsniptechnology.com:
Quote:
On Sat, 2 May 2020 16:25:57 -0400, bitrex <user_at_example.net> wrote:

On 5/2/2020 3:07 PM, jlarkin_at_highlandsniptechnology.com wrote:
On Fri, 1 May 2020 14:03:15 -0400, bitrex <user_at_example.net> wrote:

Here's the situation in simplified schematic form, generate a
high-efficiency sine wave at around 3-5MHz putting out about 5 watts
into resistive load:

https://www.dropbox.com/s/tz1zp0d8oy8zkws/IMG_20200501_133832793.jpg?dl=0

Just drive it like two half-bridges with appropriate logic-level
wavaeforms (some dead-time) and if you look at the two switching nodes
together on a plot you get the red/black waveform there under inductor
L1. LC filter it through a coupled inductor. and Bob's your Dad's uncle.
in theory.

First attempt at it on a protoboard:

https://www.dropbox.com/s/1n69o0yzhd2rbpk/Schem.PNG?dl=0

"it looks great in the sim" and the connection of the boost diodes to
the switching nodes gives a nice ~12-13 volt Vdd to common rail above
the lockout threshold for the flying driver's supply nodes and keeps all
the component dissipation low.

https://www.dropbox.com/s/sv5fox0ywcmpypv/Sine.PNG?dl=0

Total miserable nightmare to get working right as a prototype, losing
gate drivers for unknown reason, these chips seem way slower than the
~50n prop delay specified in the datasheet, can't get up to speed. I
don't think this 4120 likes being driven the way it's connected here in
reality and they're dying on me, or I've made an error in the
implementation somewhere i can't readily spot.

Anyway, I hate it, looking for any suggestions or alternate gate-drive
schemes for this, I'd like a cheaper faster and more rugged one, as
someone mentioned I don't really need the ADuM4120's internal
transformer isolation if I could find a good way to level-shift the
incoming logic level drive appropriately to the negative rails the lower
FETs have. Thanks

Something like this maybe?

https://www.dropbox.com/s/87fj0uyt8llt6hq/5W_Sine_Waves.JPG?raw=1

If you need more voltage, you could do a Colpitts sort of step-up for
the bandpass case. Takes one more cap.

Aside, I have been burned a couple of times (literally burned) by
selecting inductors that appeared to be within their ratings, but got
hot from core loss and/or skin loss.

That's happening right now on our 300 watt class-D amp. Fortunately,
it wouldn't be awful to hang some toroids on the surface-mount
inductor footprints.



Since I have the four-level drive waveforms available already how about
something like this using the IXYS chip:

https://www.dropbox.com/s/vdsoeigilgxmbrl/IMG_20200502_161215072.jpg?dl=0

The schottkeys aren't ideal but for low powers should be OK for now I
think. If they need more power at some point I can figure that out later
with a proper half-bridge drivers and external FETs.

Seems awfully complex to make a sine wave.

The IXYS part claims anti-shoot-thru features, but it might get hot at
high supply voltage and high clock rate. 5 MHz and, say, 25 volts
might not work.

Do you want 100V p-p sine at 5 MHz? Sounds like RF to me. Class C amp
maybe. 50 volt supply, one fet, LC tank.


https://www.nxp.com/products/rf/rf-power/rf-ism-and-broadcast/1-600-mhz-broadcast-and-ism/100-w-cw-over-1-8-250-mhz-50-v-wideband-rf-power-ldmos-transistor:MRF101AN

https://www.nxp.com/products/rf/rf-power/rf-ism-and-broadcast/1-600-mhz-broadcast-and-ism/300-w-cw-over-1-8-250-mhz-50-v-wideband-rf-power-ldmos-transistor:MRF300AN

bitrex
Guest

Sat May 02, 2020 11:45 pm   



On 5/2/2020 4:45 PM, jlarkin_at_highlandsniptechnology.com wrote:
Quote:
On Sat, 2 May 2020 16:25:57 -0400, bitrex <user_at_example.net> wrote:

On 5/2/2020 3:07 PM, jlarkin_at_highlandsniptechnology.com wrote:
On Fri, 1 May 2020 14:03:15 -0400, bitrex <user_at_example.net> wrote:

Here's the situation in simplified schematic form, generate a
high-efficiency sine wave at around 3-5MHz putting out about 5 watts
into resistive load:

https://www.dropbox.com/s/tz1zp0d8oy8zkws/IMG_20200501_133832793.jpg?dl=0

Just drive it like two half-bridges with appropriate logic-level
wavaeforms (some dead-time) and if you look at the two switching nodes
together on a plot you get the red/black waveform there under inductor
L1. LC filter it through a coupled inductor. and Bob's your Dad's uncle.
in theory.

First attempt at it on a protoboard:

https://www.dropbox.com/s/1n69o0yzhd2rbpk/Schem.PNG?dl=0

"it looks great in the sim" and the connection of the boost diodes to
the switching nodes gives a nice ~12-13 volt Vdd to common rail above
the lockout threshold for the flying driver's supply nodes and keeps all
the component dissipation low.

https://www.dropbox.com/s/sv5fox0ywcmpypv/Sine.PNG?dl=0

Total miserable nightmare to get working right as a prototype, losing
gate drivers for unknown reason, these chips seem way slower than the
~50n prop delay specified in the datasheet, can't get up to speed. I
don't think this 4120 likes being driven the way it's connected here in
reality and they're dying on me, or I've made an error in the
implementation somewhere i can't readily spot.

Anyway, I hate it, looking for any suggestions or alternate gate-drive
schemes for this, I'd like a cheaper faster and more rugged one, as
someone mentioned I don't really need the ADuM4120's internal
transformer isolation if I could find a good way to level-shift the
incoming logic level drive appropriately to the negative rails the lower
FETs have. Thanks

Something like this maybe?

https://www.dropbox.com/s/87fj0uyt8llt6hq/5W_Sine_Waves.JPG?raw=1

If you need more voltage, you could do a Colpitts sort of step-up for
the bandpass case. Takes one more cap.

Aside, I have been burned a couple of times (literally burned) by
selecting inductors that appeared to be within their ratings, but got
hot from core loss and/or skin loss.

That's happening right now on our 300 watt class-D amp. Fortunately,
it wouldn't be awful to hang some toroids on the surface-mount
inductor footprints.



Since I have the four-level drive waveforms available already how about
something like this using the IXYS chip:

https://www.dropbox.com/s/vdsoeigilgxmbrl/IMG_20200502_161215072.jpg?dl=0

The schottkeys aren't ideal but for low powers should be OK for now I
think. If they need more power at some point I can figure that out later
with a proper half-bridge drivers and external FETs.

Seems awfully complex to make a sine wave.

The IXYS part claims anti-shoot-thru features, but it might get hot at
high supply voltage and high clock rate. 5 MHz and, say, 25 volts
might not work.


Is there a similar chip with thermal protection? I built in plenty of
dead-time to the drive waveforms. But with a light load that the drivers
will cook off.

Quote:
Do you want 100V p-p sine at 5 MHz? Sounds like RF to me. Class C amp
maybe. 50 volt supply, one fet, LC tank.


Can't do a narrowband resonant tank, the frequency needs adjusting in
steps, the circuit is clocked.

bitrex
Guest

Sat May 02, 2020 11:45 pm   



On 5/2/2020 6:07 PM, bitrex wrote:
Quote:
On 5/2/2020 4:45 PM, jlarkin_at_highlandsniptechnology.com wrote:
On Sat, 2 May 2020 16:25:57 -0400, bitrex <user_at_example.net> wrote:

On 5/2/2020 3:07 PM, jlarkin_at_highlandsniptechnology.com wrote:
On Fri, 1 May 2020 14:03:15 -0400, bitrex <user_at_example.net> wrote:

Here's the situation in simplified schematic form, generate a
high-efficiency sine wave at around 3-5MHz putting out about 5 watts
into resistive load:

https://www.dropbox.com/s/tz1zp0d8oy8zkws/IMG_20200501_133832793.jpg?dl=0


Just drive it like two half-bridges with appropriate logic-level
wavaeforms (some dead-time) and if you look at the two switching nodes
together on a plot you get the red/black waveform there under inductor
L1. LC filter it through a coupled inductor. and Bob's your Dad's
uncle.
in theory.

First attempt at it on a protoboard:

https://www.dropbox.com/s/1n69o0yzhd2rbpk/Schem.PNG?dl=0

"it looks great in the sim" and the connection of the boost diodes to
the switching nodes gives a nice ~12-13 volt Vdd to common rail above
the lockout threshold for the flying driver's supply nodes and
keeps all
the component dissipation low.

https://www.dropbox.com/s/sv5fox0ywcmpypv/Sine.PNG?dl=0

Total miserable nightmare to get working right as a prototype, losing
gate drivers for unknown reason, these chips seem way slower than the
~50n prop delay specified in the datasheet, can't get up to speed. I
don't think this 4120 likes being driven the way it's connected
here in
reality and they're dying on me, or I've made an error in the
implementation somewhere i can't readily spot.

Anyway, I hate it, looking for any suggestions or alternate gate-drive
schemes for this, I'd like a cheaper faster and more rugged one, as
someone mentioned I don't really need the ADuM4120's internal
transformer isolation if I could find a good way to level-shift the
incoming logic level drive appropriately to the negative rails the
lower
FETs have. Thanks

Something like this maybe?

https://www.dropbox.com/s/87fj0uyt8llt6hq/5W_Sine_Waves.JPG?raw=1

If you need more voltage, you could do a Colpitts sort of step-up for
the bandpass case. Takes one more cap.

Aside, I have been burned a couple of times (literally burned) by
selecting inductors that appeared to be within their ratings, but got
hot from core loss and/or skin loss.

That's happening right now on our 300 watt class-D amp. Fortunately,
it wouldn't be awful to hang some toroids on the surface-mount
inductor footprints.



Since I have the four-level drive waveforms available already how about
something like this using the IXYS chip:

https://www.dropbox.com/s/vdsoeigilgxmbrl/IMG_20200502_161215072.jpg?dl=0


The schottkeys aren't ideal but for low powers should be OK for now I
think. If they need more power at some point I can figure that out later
with a proper half-bridge drivers and external FETs.

Seems awfully complex to make a sine wave.

The IXYS part claims anti-shoot-thru features, but it might get hot at
high supply voltage and high clock rate. 5 MHz and, say, 25 volts
might not work.

Is there a similar chip with thermal protection? I built in plenty of
dead-time to the drive waveforms. But with a light load that the drivers
will cook off.


Correction, not light load I mean heavy load/short circuit

Quote:
Do you want 100V p-p sine at 5 MHz? Sounds like RF to me. Class C amp
maybe. 50 volt supply, one fet, LC tank.


Can't do a narrowband resonant tank, the frequency needs adjusting in
steps, the circuit is clocked.




bitrex
Guest

Sat May 02, 2020 11:45 pm   



On 5/2/2020 6:11 PM, bitrex wrote:
Quote:
On 5/2/2020 6:07 PM, bitrex wrote:
On 5/2/2020 4:45 PM, jlarkin_at_highlandsniptechnology.com wrote:
On Sat, 2 May 2020 16:25:57 -0400, bitrex <user_at_example.net> wrote:

On 5/2/2020 3:07 PM, jlarkin_at_highlandsniptechnology.com wrote:
On Fri, 1 May 2020 14:03:15 -0400, bitrex <user_at_example.net> wrote:

Here's the situation in simplified schematic form, generate a
high-efficiency sine wave at around 3-5MHz putting out about 5 watts
into resistive load:

https://www.dropbox.com/s/tz1zp0d8oy8zkws/IMG_20200501_133832793.jpg?dl=0


Just drive it like two half-bridges with appropriate logic-level
wavaeforms (some dead-time) and if you look at the two switching
nodes
together on a plot you get the red/black waveform there under
inductor
L1. LC filter it through a coupled inductor. and Bob's your Dad's
uncle.
in theory.

First attempt at it on a protoboard:

https://www.dropbox.com/s/1n69o0yzhd2rbpk/Schem.PNG?dl=0

"it looks great in the sim" and the connection of the boost diodes to
the switching nodes gives a nice ~12-13 volt Vdd to common rail above
the lockout threshold for the flying driver's supply nodes and
keeps all
the component dissipation low.

https://www.dropbox.com/s/sv5fox0ywcmpypv/Sine.PNG?dl=0

Total miserable nightmare to get working right as a prototype, losing
gate drivers for unknown reason, these chips seem way slower than the
~50n prop delay specified in the datasheet, can't get up to speed. I
don't think this 4120 likes being driven the way it's connected
here in
reality and they're dying on me, or I've made an error in the
implementation somewhere i can't readily spot.

Anyway, I hate it, looking for any suggestions or alternate
gate-drive
schemes for this, I'd like a cheaper faster and more rugged one, as
someone mentioned I don't really need the ADuM4120's internal
transformer isolation if I could find a good way to level-shift the
incoming logic level drive appropriately to the negative rails the
lower
FETs have. Thanks

Something like this maybe?

https://www.dropbox.com/s/87fj0uyt8llt6hq/5W_Sine_Waves.JPG?raw=1

If you need more voltage, you could do a Colpitts sort of step-up for
the bandpass case. Takes one more cap.

Aside, I have been burned a couple of times (literally burned) by
selecting inductors that appeared to be within their ratings, but got
hot from core loss and/or skin loss.

That's happening right now on our 300 watt class-D amp. Fortunately,
it wouldn't be awful to hang some toroids on the surface-mount
inductor footprints.



Since I have the four-level drive waveforms available already how about
something like this using the IXYS chip:

https://www.dropbox.com/s/vdsoeigilgxmbrl/IMG_20200502_161215072.jpg?dl=0


The schottkeys aren't ideal but for low powers should be OK for now I
think. If they need more power at some point I can figure that out
later
with a proper half-bridge drivers and external FETs.

Seems awfully complex to make a sine wave.

The IXYS part claims anti-shoot-thru features, but it might get hot at
high supply voltage and high clock rate. 5 MHz and, say, 25 volts
might not work.

Is there a similar chip with thermal protection? I built in plenty of
dead-time to the drive waveforms. But with a light load that the
drivers will cook off.

Correction, not light load I mean heavy load/short circuit


Actually there are probs at both the way I've drawn mine. Unloaded it'll
act like a flyback. I'd better put an R in parallel with the C to damp
it if the secondary is unloadded

Jon Elson
Guest

Sun May 03, 2020 2:45 am   



bitrex wrote:

Quote:
Here's the situation in simplified schematic form, generate a
high-efficiency sine wave at around 3-5MHz putting out about 5 watts
into resistive load:

You want to generate a 5 MHz sine wave with PWM? What kind of PWM frequency
would you need for that? 50 MHz?

Look up the gate driver specs for dissipation, and you will likely see NONE
of them can handle charging and discharging a FET gate at much over 100 KHz
rates without running very hot.

One other thing I ran into while designing full bridge PWM amps was that the
FET body diodes take microseconds to turn on, but when the high-side
transistor cuts off, current flowing out through the inductor needs to be
supplied from somewhere. The body diodes can easily sit there for several
microseconds with a forward bias of 7 - 12 V without conducting at all.
So, I had to add an ultrafast diode across the low-side transistor to
prevent the common node from going too far negative. Many gate drivers can
only handle the common node going so far below ground before they pop.

Jon

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