Goto page 1, 2 Next
Brad Smallridge
Guest
Fri Feb 19, 2010 1:14 am
Hello VHDL group,
I have a need to translate a natural generic
into a 0 or 1 constant something like:
entity . . .
generic(sim : natural . . .
port( ...
constant sim01 : natural := 0 if sim=0, else :=1;
.. . .
begin
.. . .
but of course this syntax doesn't fly.
Brad
Mike Treseler
Guest
Fri Feb 19, 2010 1:48 am
Brad Smallridge wrote:
Quote:
constant sim01 : natural := 0 if sim=0, else :=1;
how about
constant sim_c : boolean := sim=1;
KJ
Guest
Fri Feb 19, 2010 5:37 am
On Feb 18, 7:14 pm, "Brad Smallridge" <bradsmallri...@dslextreme.com>
wrote:
Quote:
Hello VHDL group,
I have a need to translate a natural generic
into a 0 or 1 constant something like:
entity . . .
generic(sim : natural . . .
port( ...
constant sim01 : natural := 0 if sim=0, else :=1;
. . .
begin
. . .
but of course this syntax doesn't fly.
Brad
Sometimes I find I like 'C' where you can implement a 2->1 selection
quite concisely
c = cond: a ? b; (at least I think that's the syntax).
So much so, that I create a select function 'sel' that works
similarly...and then override it to work with all the basic data types
function sel(Cond: BOOLEAN; A, B: integer) return integer;
function sel(Cond: BOOLEAN; A, B: real) return real;
function sel(Cond: BOOLEAN; A, B: time) return time;
etc.
function sel(Cond: std_ulogic; A, B: integer) return integer;
function sel(Cond: std_ulogic; A, B: real) return real;
function sel(Cond: std_ulogic; A, B: time) return time;
etc.
While it's a bit of pain (but only one time) to create these headers,
the function body itself is a straight copy and paste with virtually
no editing for each variant.
begin
if (Cond = '1') then
return(A);
else
return(B);
end if;
end function sel;
I package that all up in a package with other generally useful
functions that I routinely use so that for the example you want, I can
simply say
constant sim01 : natural := sel(sim, 0,1);
Kevin Jennings
Jonathan Bromley
Guest
Fri Feb 19, 2010 11:47 am
On Thu, 18 Feb 2010 16:14:48 -0800, "Brad Smallridge"
<bradsmallridge_at_dslextreme.com> wrote:
Quote:
Hello VHDL group,
I have a need to translate a natural generic
into a 0 or 1 constant something like:
entity . . .
generic(sim : natural . . .
port( ...
constant sim01 : natural := 0 if sim=0, else :=1;
function to_yucky_C_truth_value(b: boolean)
return integer
is
begin
if b then return 1; else return 0; end if;
end
constant
sim01: natural := to_yucky_C_truth_value(sim/=0);
OK?
--
Jonathan Bromley
Brian Drummond
Guest
Fri Feb 19, 2010 12:47 pm
On Thu, 18 Feb 2010 19:37:37 -0800 (PST), KJ <kkjennings_at_sbcglobal.net> wrote:
Quote:
Sometimes I find I like 'C' where you can implement a 2->1 selection
quite concisely
c = cond: a ? b; (at least I think that's the syntax).
For some reason when I see this syntax I expect it to select the values from
left to right according to increasing values of cond.
funnily enough I don't get along with C very well...
- Brian
Dave Higton
Guest
Fri Feb 19, 2010 9:21 pm
In message <sbusn51orumfojm92gporo70ef0v80e43p_at_4ax.com>
Brian Drummond <brian_drummond_at_btconnect.com> wrote:
Quote:
On Thu, 18 Feb 2010 19:37:37 -0800 (PST), KJ <kkjennings_at_sbcglobal.net
wrote:
Sometimes I find I like 'C' where you can implement a 2->1 selection
quite concisely
c = cond: a ? b; (at least I think that's the syntax).
No...
Quote:
For some reason when I see this syntax I expect it to select the values
from left to right according to increasing values of cond.
c = cond ? a : b;
is it true? yes or no
That's my method of remembering it.
Dave
JimLewis
Guest
Fri Feb 19, 2010 10:37 pm
Quote:
constant sim01 : natural := 0 if sim=0, else :=1;
constant sim01 : natural := 1 - boolean'pos(sim=0) ;
-- disclaimer, I have not compiled this code and I
-- have not tried this in a synthesis tool.
Writing a function would make this more readable.
Perhaps one that has a natural typed input.
Pretty easy case statement.
Quote:
c = cond: a ? b; (at least I think that's the syntax).
No...
For some reason when I see this syntax I expect it to select the values
from left to right according to increasing values of cond.
c = cond ? a : b;
is it true? yes or no
For VHDL-2008, we had a proposal for the following:
constant sim01 : natural := 0 if sim = 0 else 1 ;
it got modified to be:
constant sim01 : natural := 0 if sim = 0, 1 ;
which then got rejected due to ambiguity.
With user backing, it would not be difficult to revive the
first proposal but we really need more participating
in the standards effort to make this happen.
Furthermore to keep VHDL growing, we would also need
to add more verification features to bring it up to
system verilog capability. Since VHDL already has
things like protected types, it is not a huge step -
we just need more user backing.
Best,
Jim
JimLewis
Guest
Fri Feb 19, 2010 10:42 pm
Quote:
For VHDL-2008, we had a proposal for the following:
constant sim01 : natural := 0 if sim = 0 else 1 ;
it got modified to be:
constant sim01 : natural := 0 if sim = 0, 1 ;
which then got rejected due to ambiguity.
Reflecting on the other posts, I probably like
KJ's post better than adding the if to the language.
I would probably call it Mux2 rather than Sel though.
I would probably also create a Mux4 at the same time.
It would be nice to have a set of these type of
functions in a standard package. Unfortunately if
we did that through IEEE, they would not allow
vendors to publish source code without paying
around $50K to IEEE.
Best,
Jim
Mike Treseler
Guest
Fri Feb 19, 2010 11:40 pm
Quote:
On Feb 19, 4:44 pm, ralphmalph <arius....@gmail.com> wrote:
Maybe I am missing something, I'm not always up on what works and what
doesn't work in VHDL. But why can't you directly assign the generic
to the constant? Does that not work?
Ahh yes, but that would not distract me from my work.
KJ wrote:
Quote:
Well actually you're right, you CAN assign the generic directly to the
constant...but I *think* what Brad intended in the original post was
that 'sim' was either a boolean or std_logic, not a number and he
wants to come out then with a number representing it...at least that's
the way I misinterpreted it to be.
I share your prejudice for the interesting interpretation ;)
-- Mike Treseler
ralphmalph
Guest
Fri Feb 19, 2010 11:44 pm
On Feb 18, 7:14 pm, "Brad Smallridge" <bradsmallri...@dslextreme.com>
wrote:
Quote:
Hello VHDL group,
I have a need to translate a natural generic
into a 0 or 1 constant something like:
entity . . .
generic(sim : natural . . .
port( ...
constant sim01 : natural := 0 if sim=0, else :=1;
. . .
begin
. . .
but of course this syntax doesn't fly.
Brad
Maybe I am missing something, I'm not always up on what works and what
doesn't work in VHDL. But why can't you directly assign the generic
to the constant? Does that not work?
entity . . .
generic(sim : natural . . .
port( ...
constant sim01 : natural := sim;
I know VHDL has a lot of issues having to do with when the tools know
what, so the generic might not be available when you need to define
the constant. But if that is the case, no method would work, right?
Rick
KJ
Guest
Fri Feb 19, 2010 11:50 pm
On Feb 19, 3:42 pm, JimLewis <J...@SynthWorks.com> wrote:
Quote:
Reflecting on the other posts, I probably like
KJ's post better than adding the if to the language.
I would probably call it Mux2 rather than Sel though.
I would've called the function 'select', but that keyword was already
taken.
KJ
KJ
Guest
Fri Feb 19, 2010 11:54 pm
On Feb 19, 4:44 pm, ralphmalph <arius....@gmail.com> wrote:
Quote:
Maybe I am missing something, I'm not always up on what works and what
doesn't work in VHDL. But why can't you directly assign the generic
to the constant? Does that not work?
Well actually you're right, you CAN assign the generic directly to the
constant...but I *think* what Brad intended in the original post was
that 'sim' was either a boolean or std_logic, not a number and he
wants to come out then with a number representing it...at least that's
the way I misinterpreted it to be.
KJ
Brad Smallridge
Guest
Mon Feb 22, 2010 3:06 am
OK, what I'm hearing is that I need a function
to make the conversion.
I do need a natural because I use it
as an argument in various arrays. I believe,
that a boolean wouldn't work as an argument
for an array.
I had been setting sim to 0 or 1 but now
I would like to send more options
to the various modules under simulation.
Perhaps have several arrays of sim values.
Thanks all for the advice.
Quote:
I have a need to translate a natural generic
into a 0 or 1 constant something like:
entity . . .
generic(sim : natural . . .
port( ...
constant sim01 : natural := 0 if sim=0, else :=1;
. . .
begin
. . .
but of course this syntax doesn't fly.
Brad
Jonathan Bromley
Guest
Mon Feb 22, 2010 3:38 am
On Sun, 21 Feb 2010 18:06:24 -0800, "Brad Smallridge" wrote:
Quote:
OK, what I'm hearing is that I need a function
to make the conversion.
I do need a natural because I use it
as an argument in various arrays. I believe,
that a boolean wouldn't work as an argument
for an array.
Why not? Not if you're trying to index into
a std_logic_vector, of course, but if you can
make a custom array type then it's perfectly
OK for the subscript to be a boolean. Suppose,
for example, you wanted to have an array of
two integers indexed by boolean.
type my_array_type is
array (boolean) of integer;
signal chooser: my_array_type;
signal result: integer;
...
chooser(TRUE) <= 55;
chooser(FALSE) <= 100;
...
result <= chooser(A >= B);
-- result=55 if A>=B, result=100 if not.
Any boolean expression will do as the subscript.
Nice, or what?
--
Jonathan Bromley
Andy
Guest
Mon Feb 22, 2010 10:36 pm
On Feb 19, 3:50 pm, KJ <kkjenni...@sbcglobal.net> wrote:
Quote:
On Feb 19, 3:42 pm, JimLewis <J...@SynthWorks.com> wrote:
Reflecting on the other posts, I probably like
KJ's post better than adding the if to the language.
I would probably call it Mux2 rather than Sel though.
I would've called the function 'select', but that keyword was already
taken.
KJ
I prefer KJ's sel(), but maybe with argument names like if_true, and
if_false, so you could call it with this:
sel(sim = 0, if_true => 0, if_false => 1);
I also like the constant boolean-indexed array that Jonathan proposed.
Andy
Goto page 1, 2 Next