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generate VHDL testbench from requirements

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Bobby
Guest

Sun Sep 02, 2018 12:45 am   



Hi

I have a very simple VHDL as my DUT (device under test). I would like to generate a VHDL test bench for this DUT based on the 'requirements'. I wrote its (DUT) functions in simple text as 'requirements' . Now through the help of my grammar, I can give the requirement input to my grammar to generate a parser in Java or Python.

Questions:

(1) Considering my end goal, i.e. to generate VHDL TB,
a java parser would be better or python ?

(2) Given the generated python parser from grammar,
will any kind of python scripting will help me to generate
the testbench in VHDL for my DUT ? My confusion at this point
is that most of all the literature I am reading
suggests linguistic techniques. Any non-linguistic technique ?



(3) Any technique to go on further with java parser ?


Looking forward for suggestions Smile

Thomas Stanka
Guest

Tue Sep 04, 2018 11:45 am   



Am Sonntag, 2. September 2018 01:01:19 UTC+2 schrieb Bobby:
Quote:
I have a very simple VHDL as my DUT (device under test). I would like to generate a VHDL test bench for this DUT based on the 'requirements'. I wrote its (DUT) functions in simple text as 'requirements' . Now through the help of my grammar, I can give the requirement input to my grammar to generate a parser in Java or Python.

Questions:

(1) Considering my end goal, i.e. to generate VHDL TB,
a java parser would be better or python ?

(2) Given the generated python parser from grammar,
will any kind of python scripting will help me to generate
the testbench in VHDL for my DUT ? My confusion at this point
is that most of all the literature I am reading
suggests linguistic techniques. Any non-linguistic technique ?


For writing a parser I would prefer python over java, but in the end take the one you think will provide best results from you.

The more interessting point is converting requirements in a testbench.
Even if you formulated your requirements biunique so parsing will lead to correct "understanding", I feel it very hard to formulate general testbench structures. Maybe it is possible to convert them in assertions, but ensuring a testcase is triggering an assertion is farm from beeing simple unless you have a very specific set of assertions (eg. trigger A leads to response B within C clock cycles).

regards,

Thomas

Bobby
Guest

Tue Sep 04, 2018 11:45 pm   



Hi Thomas

Though I discussed these questions verbally with some colleagues, but so far the most reasonable reply I got is from you. Thanks ! your points make sense..... I also thought on these points i.e. 'assertions'. May be System Verilog assertions can also be considered.

I would really be interested to know why you consider python better than java for writing parser ?



On Tuesday, September 4, 2018 at 12:03:06 PM UTC+2, Thomas Stanka wrote:
Quote:
Am Sonntag, 2. September 2018 01:01:19 UTC+2 schrieb Bobby:
I have a very simple VHDL as my DUT (device under test). I would like to generate a VHDL test bench for this DUT based on the 'requirements'. I wrote its (DUT) functions in simple text as 'requirements' . Now through the help of my grammar, I can give the requirement input to my grammar to generate a parser in Java or Python.

Questions:

(1) Considering my end goal, i.e. to generate VHDL TB,
a java parser would be better or python ?

(2) Given the generated python parser from grammar,
will any kind of python scripting will help me to generate
the testbench in VHDL for my DUT ? My confusion at this point
is that most of all the literature I am reading
suggests linguistic techniques. Any non-linguistic technique ?

For writing a parser I would prefer python over java, but in the end take the one you think will provide best results from you.

The more interessting point is converting requirements in a testbench.
Even if you formulated your requirements biunique so parsing will lead to correct "understanding", I feel it very hard to formulate general testbench structures. Maybe it is possible to convert them in assertions, but ensuring a testcase is triggering an assertion is farm from beeing simple unless you have a very specific set of assertions (eg. trigger A leads to response B within C clock cycles).

regards,

Thomas


Thomas Stanka
Guest

Tue Sep 11, 2018 2:45 pm   



Am Mittwoch, 5. September 2018 00:42:11 UTC+2 schrieb Bobby:
Quote:
Hi Thomas

Though I discussed these questions verbally with some colleagues, but so far the most reasonable reply I got is from you. Thanks ! your points make sense..... I also thought on these points i.e. 'assertions'. May be System Verilog assertions can also be considered.


For assertions you could even use VHDL. System Verilog and PSL just provide additional syntax to reduce the code overhead. But they require learning new syntax and may requrie more expensive licenses for the tools.

The general problem is how to convert general requirements in some formal standardized test. This is very depending on the question how your requirements look alike.

For every code you write I am sure you will find a document called "Specification" that will not work for your approach.

I guess it is far easier to define a certain set of requirements in a structured way that can be parsed and converted than writing code for a general requirement specification.

> I would really be interested to know why you consider python better than java for writing parser ?

My java experience is maybe outdated (mostly last century), but read in a string from file and parse it for its contents was then something consuming far more code effort than in python.

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