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silverdr
Guest

Wed Jun 15, 2016 5:41 pm   



Hello group (and please have understanding for a newbie in the subject).

I'd like to make use of GAL chips for a relatively simple logic I need to build. Nine inputs to five outputs, purely combinatorial, non-clocked. I wrote VHDL design and testbench and successfully tested it on edaplayground.com. Now, I'd like to synthesise it and then comes some questions:

- what software (preferably but not necessarily free as in speech and open-source) should I use for that? I have 16V8 and 20V8 chips from Lattice, Atmel and one or two more vendors (don't remember exactly now).

- are the synthesised files compatible across different vendors' chips?

- If there is a GAL (16V8 for example) which has eight inputs and eight Output Logic MacroCells, can some of those OLMCs/pins be configured and used as inputs too? Judging by the specs/datasheet "yes" but would like to confirm that.


So far I downloaded and installed the ispLEVER from Lattice, which is still available and supports "obsolete" devices like GALs. The problem is that when I try to do some synthesis using ispLEVER/PureVHDL/Synplify/ project I get output like:

*******
Starting: 'C:\ispLEVER_Classic2_0\ispcpld\bin\Synpwrap.exe -e r512vhdl -target ispGAL -pro '


Copyright (c) 1991-2010 Lattice Semiconductor Corporation, All rights reserved.
Version : 2.0.00.17.20.15

Done sucessfully with exit code 1.
Error output EDIF file c:/documents and settings/silverdr/my documents/sources/vhdl/r512/r512vhdl.edi
Error executing Synplicity VHDL/Verilog HDL Synthesizer with code 2

Done: failed with exit code: 0002.
*******

and am stuck at it.

I know there is a CUPL software available from Atmel, and it should be able to synthesise designs for GALs but I would prefer to stick to VHDL, which I assume is going to stay with me for some time to come. Therefore rewriting the design into CUPL is probably the last resort.

I'd be grateful for some clues/hints/pointers.

--
silverdr

rickman
Guest

Thu Jun 16, 2016 3:02 am   



On 6/15/2016 11:41 AM, silverdr wrote:
Quote:
Hello group (and please have understanding for a newbie in the subject).

I'd like to make use of GAL chips for a relatively simple logic I need to build. Nine inputs to five outputs, purely combinatorial, non-clocked. I wrote VHDL design and testbench and successfully tested it on edaplayground.com. Now, I'd like to synthesise it and then comes some questions:

- what software (preferably but not necessarily free as in speech and open-source) should I use for that? I have 16V8 and 20V8 chips from Lattice, Atmel and one or two more vendors (don't remember exactly now).

- are the synthesised files compatible across different vendors' chips?

- If there is a GAL (16V8 for example) which has eight inputs and eight Output Logic MacroCells, can some of those OLMCs/pins be configured and used as inputs too? Judging by the specs/datasheet "yes" but would like to confirm that.


So far I downloaded and installed the ispLEVER from Lattice, which is still available and supports "obsolete" devices like GALs. The problem is that when I try to do some synthesis using ispLEVER/PureVHDL/Synplify/ project I get output like:

*******
Starting: 'C:\ispLEVER_Classic2_0\ispcpld\bin\Synpwrap.exe -e r512vhdl -target ispGAL -pro '


Copyright (c) 1991-2010 Lattice Semiconductor Corporation, All rights reserved.
Version : 2.0.00.17.20.15

Done sucessfully with exit code 1.
Error output EDIF file c:/documents and settings/silverdr/my documents/sources/vhdl/r512/r512vhdl.edi
Error executing Synplicity VHDL/Verilog HDL Synthesizer with code 2

Done: failed with exit code: 0002.
*******

and am stuck at it.

I know there is a CUPL software available from Atmel, and it should be able to synthesise designs for GALs but I would prefer to stick to VHDL, which I assume is going to stay with me for some time to come. Therefore rewriting the design into CUPL is probably the last resort.

I'd be grateful for some clues/hints/pointers.


There should be a window with more information including the detail of
what error was found. I don't run the classic version of the Lattice
tools, but nose around the interface a bit and see if you can find the
report. In Diamond there is a "Design Summary" window where you can get
reports under "Process Reports" by clicking the tool name. Look for
something smilar.

--

Rick C

Thomas Stanka
Guest

Thu Jun 16, 2016 3:37 pm   



Am Mittwoch, 15. Juni 2016 17:41:35 UTC+2 schrieb silverdr:
Quote:
I'd like to make use of GAL chips for a relatively simple logic I need to build. Nine inputs to five outputs, purely combinatorial, non-clocked. I wrote VHDL design and testbench and successfully tested it on edaplayground.com. Now, I'd like to synthesise it and then comes some questions:

- what software (preferably but not necessarily free as in speech and open-source) should I use for that? I have 16V8 and 20V8 chips from Lattice, Atmel and one or two more vendors (don't remember exactly now).

- are the synthesised files compatible across different vendors' chips?


In usual meaning No.

Synthesis means usually you translate a v(hdl) description into a library dependend structural netlist containing only library primitives of the target library. The tool usually translate it first in a generic (target independent) netlist and converts than to a library dependen netlist but for the user the intermediate result is not accessible.

Especially the "free" (in terms of no cost) versions that are available from major FPGA vendors allow only the usage of dedicated libraries, while a full blown synthesizer license would usually allow to include self written libraries (and therefore the possibility eg to write out a netlist converted in NAND2, if you design a library containing only nand2 and Flipflop).


Quote:
Error output EDIF file c:/documents and settings/silverdr/my documents/sources/vhdl/r512/r512vhdl.edi
Error executing Synplicity VHDL/Verilog HDL Synthesizer with code 2


This might be related to an error in your vhdl description. Impossible for me to guess why this error is generated.

KJ
Guest

Thu Jun 16, 2016 4:17 pm   



On Wednesday, June 15, 2016 at 11:41:35 AM UTC-4, silverdr wrote:
Quote:

- are the synthesised files compatible across different vendors' chips?

For PAL/GAL devices, the synthesis output file is a JEDEC file that is used to program the device. For those devices, the JEDEC files were not vendor specific.


Kevin Jennings

KJ
Guest

Thu Jun 16, 2016 4:20 pm   



On Thursday, June 16, 2016 at 9:37:21 AM UTC-4, Thomas Stanka wrote:
Quote:
Am Mittwoch, 15. Juni 2016 17:41:35 UTC+2 schrieb silverdr:

- are the synthesised files compatible across different vendors' chips?

In usual meaning No.

Synthesis means usually you translate a v(hdl) description into a library
dependend structural netlist containing only library primitives of the
target library. The tool usually translate it first in a generic (target
independent) netlist and converts than to a library dependen netlist but
for the user the intermediate result is not accessible.


What you described isn't really the case with PAL/GAL devices that the OP was referencing. The output of synthesis for these devices is a JEDEC file which typically could be used to program the device regardless of the vendor.

Kevin Jennings

silverdr
Guest

Thu Jun 16, 2016 5:32 pm   



On Wednesday, 15 June 2016 23:02:10 UTC+2, rickman wrote:
Quote:
So far I downloaded and installed the ispLEVER from Lattice, which is still available and supports "obsolete" devices like GALs. The problem is that when I try to do some synthesis using ispLEVER/PureVHDL/Synplify/ project I get output like:

*******
Starting: 'C:\ispLEVER_Classic2_0\ispcpld\bin\Synpwrap.exe -e r512vhdl -target ispGAL -pro '


Copyright (c) 1991-2010 Lattice Semiconductor Corporation, All rights reserved.
Version : 2.0.00.17.20.15

Done sucessfully with exit code 1.
Error output EDIF file c:/documents and settings/silverdr/my documents/sources/vhdl/r512/r512vhdl.edi
Error executing Synplicity VHDL/Verilog HDL Synthesizer with code 2

Done: failed with exit code: 0002.
*******


There should be a window with more information including the detail of
what error was found. I don't run the classic version of the Lattice
tools, but nose around the interface a bit and see if you can find the
report. In Diamond there is a "Design Summary" window where you can get
reports under "Process Reports" by clicking the tool name. Look for
something smilar.


Actually the above is the copy-paste from the only output (except dialog-box, which says even less) I can find.

silverdr
Guest

Thu Jun 16, 2016 5:44 pm   



On Thursday, 16 June 2016 15:28:27 UTC+2, Gabor Sz wrote:

Quote:
- what software (preferably but not necessarily free as in speech and open-source) should I use for that? I have 16V8 and 20V8 chips from Lattice, Atmel and one or two more vendors (don't remember exactly now).


It's been at about 20 years since I used these, so most of the software
I remember is long gone. Cypress used to have a free VHDL for PALs.


I tried also "Galaxy WARP 6.3 SP1" from Cypress. Here things go a lot better. It compiles and outputs a JEDEC file but this is for PAL with a most similar name/symbol. Not for GAL and I have no idea whether this file can be safely used. I am sure it doesn't take into account any GAL specific stuff.

Quote:
- are the synthesised files compatible across different vendors' chips?

In the very old days there were PALs, one-time fuse-programmable devices
that came from multiple sources and used a standard JEDEC file format to
program. These were interchangeable from a code standpoint, although
your PAL programmer needed to know about the vendor.

Later Lattice came out with GALs and others copied them with devices
called PALCEs. Again the JEDEC files were similar. Most vendors had
software that would allow you to take a standard PAL JEDEC and convert
it to the GAL / PALCE format. Of course this reduces the flexibility
of the chip, since the original PALs had a fixed number of inputs and
outputs, as well as a fixed number of output registers.


I see - that's a trail I might have a look into if nothing else works. Well, I don't know if this one is going to work at all either. So far I don't have any tools for converting the PAL JEDEC (which I seem to have from the Cypress Galaxy WARP software) into GAL/PALCE format.

Quote:
- If there is a GAL (16V8 for example) which has eight inputs and eight Output Logic MacroCells, can some of those OLMCs/pins be configured and used as inputs too? Judging by the specs/datasheet "yes" but would like to confirm that.


Any I/O pin on the GAL can be used as an input. This is different from
the old PALs where only the non-registered output pins had feedback from
the pin.


Thanks. That's more or less what I thought, yet - just to make sure - does that mean that on a GAL16V8 I could theoretically use fifteen inputs and have one output only? Or are there any other limitations, which would prevent that kind of use?

Quote:
I know there is a CUPL software available from Atmel, and it should be able to synthesise designs for GALs but I would prefer to stick to VHDL, which I assume is going to stay with me for some time to come. Therefore rewriting the design into CUPL is probably the last resort.

I don't remember using CUPL, although I have used similar languages like
Abel, MachXL, and PALASM. Xilinx ISE allows you to target a CPLD like
their XC9500-series, which have a PAL-like architecture. Then you can
synthesize your VHDL, "fit" the device and view the resulting equations
in Abel syntax. These equations are reduced to sum-of-products, so you
can easily see how many product terms are used. I suppose if you are
lucky, you can then throw those equations into the Atmel software and
target your GAL. Seems like a lot more work than you want, though.


Huh.. yes. I was kind of expecting that I can get the output for my specific chip, fiddling with VHDL only Wink

silverdr
Guest

Thu Jun 16, 2016 6:01 pm   



On Thursday, 16 June 2016 15:37:21 UTC+2, Thomas Stanka wrote:

Quote:
- are the synthesised files compatible across different vendors' chips?

In usual meaning No.

Synthesis means usually you translate a v(hdl) description into a library dependend structural netlist containing only library primitives of the target library. The tool usually translate it first in a generic (target independent) netlist and converts than to a library dependen netlist but for the user the intermediate result is not accessible.

Especially the "free" (in terms of no cost) versions that are available from major FPGA vendors allow only the usage of dedicated libraries, while a full blown synthesizer license would usually allow to include self written libraries (and therefore the possibility eg to write out a netlist converted in NAND2, if you design a library containing only nand2 and Flipflop).


I am aware that if we talk about CPLDs/FPGAs, then those are not compatible, output files are not compatible and I'd possibly be lucky if VHDL source files were compatible without any adaptations ;-)

But I am not talking about CPLDs/FPGAs but "standardised" SPLDs, namely GALs. They seem to be compatible across different vendors. Might not be programmed the same way though. Which is what I ask about.

Because when I eventually get my designs synthesised somehow by /some/ software from /a/ vendor, I'd like to use the chips I have from different manufacturers. Obviously it wouldn't be much of an issue if the making the software work and output something usable wasn't such a PITA as I experienced so far.

> This might be related to an error in your vhdl description. Impossible for me to guess why this error is generated.

We're in the same boat. I can post the vhdl if that helps - it's almost a kind of "Hello, world!" though and both edaplayground and Cypress Galaxy don't complain

-- Design for RL512
library IEEE;
use IEEE.std_logic_1164.all;

entity RL512 is port(
kl : in std_logic;
ksw1 : in std_logic;
ksw0 : in std_logic;
cm : in std_logic;
csw1 : in std_logic;
csw0 : in std_logic;
bc : in std_logic;
bsw0 : in std_logic;
a12m : in std_logic;
oe : out std_logic;
a15 : out std_logic;
a14 : out std_logic;
a13 : out std_logic;
a12 : out std_logic);

--attribute pin_numbers of RL512:entity is
-- "kl:2 ksw1:3 ksw0:4 cm:5 csw1:6 csw0:7 bc:8 bsw0:9 a12m:18 "
-- & "oe:19 a15:15 a14:14 a13:13 a12:12";

end RL512;

architecture rl512_behavioral of RL512 is
begin
oe <= kl and cm and bc;

a15 <= not kl when ((kl = '0') or (cm = '0') or (bc = '0')) else
'Z';

a14 <= ksw1 when kl = '0' else
'1' when cm = '0' else
'0' when bc = '0' else
'Z';

a13 <= ksw0 when kl = '0' else
csw1 when cm = '0' else
bsw0 when bc = '0' else
'Z';

a12 <= a12m when kl ='0' else
csw0 when cm = '0' else
a12m when bc = '0' else
'Z';
end rl512_behavioral;

silverdr
Guest

Thu Jun 16, 2016 6:06 pm   



On Thursday, 16 June 2016 16:17:34 UTC+2, KJ wrote:
Quote:
On Wednesday, June 15, 2016 at 11:41:35 AM UTC-4, silverdr wrote:

- are the synthesised files compatible across different vendors' chips?

For PAL/GAL devices, the synthesis output file is a JEDEC file that is used to program the device. For those devices, the JEDEC files were not vendor specific.


Thanks! That's the only good news so far Smile So theoretically I should be able to use the PAL output from Cypress Galaxy WARP (which is the only one that produced something so far), somehow (yeah..) convert it into another form of JEDEC file in a GAL format and then use to program all the GALs of one main type I have (like all 16V8 in my case here), right?

silverdr
Guest

Thu Jun 16, 2016 6:16 pm   



On Thursday, 16 June 2016 17:44:49 UTC+2, rickman wrote:

Quote:

There will be a synthesis report somewhere. You just need to find it.
The exit error code tells you not so much. Your output above says it is
running Synplicity. Look for the design directories and sort the files
by date. The report will be one of the most recent.


The most recent is the automake.log, which contains what I quoted. It's followed by .TCL and .PRJ and .JID files, which don't seem to contain anything useful in the context. Unless it throws that report somewhere into a darkest corner of the harddrive, I don't see anything else.

> Have you checked for licensing issues?

Maybe I don't know how but I haven't noticed anything about licensing. I can view the EULA (from 2012 - not so old) and nothing complains about licensing.

KJ
Guest

Thu Jun 16, 2016 6:47 pm   



On Thursday, June 16, 2016 at 12:06:46 PM UTC-4, silverdr wrote:
Quote:
For PAL/GAL devices, the synthesis output file is a JEDEC file that is
used to program the device. For those devices, the JEDEC files were not
vendor specific.

Thanks! That's the only good news so far Smile So theoretically I should be
able to use the PAL output from Cypress Galaxy WARP (which is the only one
that produced something so far), somehow (yeah..) convert it into another
form of JEDEC file in a GAL format and then use to program all the GALs of
one main type I have (like all 16V8 in my case here), right?


I don't know that you can take the JEDEC file of one device and use it on a different one (i.e. 16R8 JEDEC file using on a 16V8). What I said was that you can take a JEDEC file and use it with any manufacturer's same device (i.e. Cypress 16V8 using on a Lattice 16V8).

Having said that though, it might be that you can take a 16R8 and use it to program a 16V8. When the GAL devices were first coming out in the 80s there were lots of manufacturers of SPLDs and competition. I wouldn't consider it to much of a stretch to think that Lattice V8 did accept a JEDEC file that originally was intended for an MMI 16R8 since it would allow them to grab market share even more easily. I just remember if that was the case or not. The parts are very similar after all.

Kevin Jennings

GaborSzakacs
Guest

Thu Jun 16, 2016 7:26 pm   



silverdr wrote:
Quote:
Hello group (and please have understanding for a newbie in the subject).

I'd like to make use of GAL chips for a relatively simple logic I need to build. Nine inputs to five outputs, purely combinatorial, non-clocked. I wrote VHDL design and testbench and successfully tested it on edaplayground.com. Now, I'd like to synthesise it and then comes some questions:

- what software (preferably but not necessarily free as in speech and open-source) should I use for that? I have 16V8 and 20V8 chips from Lattice, Atmel and one or two more vendors (don't remember exactly now).


It's been at about 20 years since I used these, so most of the software
I remember is long gone. Cypress used to have a free VHDL for PALs.

Quote:
- are the synthesised files compatible across different vendors' chips?


In the very old days there were PALs, one-time fuse-programmable devices
that came from multiple sources and used a standard JEDEC file format to
program. These were interchangeable from a code standpoint, although
your PAL programmer needed to know about the vendor.

Later Lattice came out with GALs and others copied them with devices
called PALCEs. Again the JEDEC files were similar. Most vendors had
software that would allow you to take a standard PAL JEDEC and convert
it to the GAL / PALCE format. Of course this reduces the flexibility
of the chip, since the original PALs had a fixed number of inputs and
outputs, as well as a fixed number of output registers.

Quote:
- If there is a GAL (16V8 for example) which has eight inputs and eight Output Logic MacroCells, can some of those OLMCs/pins be configured and used as inputs too? Judging by the specs/datasheet "yes" but would like to confirm that.


Any I/O pin on the GAL can be used as an input. This is different from
the old PALs where only the non-registered output pins had feedback from
the pin.

Quote:

So far I downloaded and installed the ispLEVER from Lattice, which is still available and supports "obsolete" devices like GALs. The problem is that when I try to do some synthesis using ispLEVER/PureVHDL/Synplify/ project I get output like:

*******
Starting: 'C:\ispLEVER_Classic2_0\ispcpld\bin\Synpwrap.exe -e r512vhdl -target ispGAL -pro '


Copyright (c) 1991-2010 Lattice Semiconductor Corporation, All rights reserved.
Version : 2.0.00.17.20.15

Done sucessfully with exit code 1.
Error output EDIF file c:/documents and settings/silverdr/my documents/sources/vhdl/r512/r512vhdl.edi
Error executing Synplicity VHDL/Verilog HDL Synthesizer with code 2

Done: failed with exit code: 0002.
*******

and am stuck at it.

I know there is a CUPL software available from Atmel, and it should be able to synthesise designs for GALs but I would prefer to stick to VHDL, which I assume is going to stay with me for some time to come. Therefore rewriting the design into CUPL is probably the last resort.

I'd be grateful for some clues/hints/pointers.


I don't remember using CUPL, although I have used similar languages like
Abel, MachXL, and PALASM. Xilinx ISE allows you to target a CPLD like
their XC9500-series, which have a PAL-like architecture. Then you can
synthesize your VHDL, "fit" the device and view the resulting equations
in Abel syntax. These equations are reduced to sum-of-products, so you
can easily see how many product terms are used. I suppose if you are
lucky, you can then throw those equations into the Atmel software and
target your GAL. Seems like a lot more work than you want, though.

--
Gabor

rickman
Guest

Thu Jun 16, 2016 9:44 pm   



On 6/16/2016 11:32 AM, silverdr wrote:
Quote:
On Wednesday, 15 June 2016 23:02:10 UTC+2, rickman wrote:
So far I downloaded and installed the ispLEVER from Lattice, which is still available and supports "obsolete" devices like GALs. The problem is that when I try to do some synthesis using ispLEVER/PureVHDL/Synplify/ project I get output like:

*******
Starting: 'C:\ispLEVER_Classic2_0\ispcpld\bin\Synpwrap.exe -e r512vhdl -target ispGAL -pro '


Copyright (c) 1991-2010 Lattice Semiconductor Corporation, All rights reserved.
Version : 2.0.00.17.20.15

Done sucessfully with exit code 1.
Error output EDIF file c:/documents and settings/silverdr/my documents/sources/vhdl/r512/r512vhdl.edi
Error executing Synplicity VHDL/Verilog HDL Synthesizer with code 2

Done: failed with exit code: 0002.
*******


There should be a window with more information including the detail of
what error was found. I don't run the classic version of the Lattice
tools, but nose around the interface a bit and see if you can find the
report. In Diamond there is a "Design Summary" window where you can get
reports under "Process Reports" by clicking the tool name. Look for
something smilar.


Actually the above is the copy-paste from the only output (except dialog-box, which says even less) I can find.


There will be a synthesis report somewhere. You just need to find it.
The exit error code tells you not so much. Your output above says it is
running Synplicity. Look for the design directories and sort the files
by date. The report will be one of the most recent.

Have you checked for licensing issues?

--

Rick C

rickman
Guest

Thu Jun 16, 2016 11:06 pm   



On 6/16/2016 12:16 PM, silverdr wrote:
Quote:
On Thursday, 16 June 2016 17:44:49 UTC+2, rickman wrote:


There will be a synthesis report somewhere. You just need to find it.
The exit error code tells you not so much. Your output above says it is
running Synplicity. Look for the design directories and sort the files
by date. The report will be one of the most recent.

The most recent is the automake.log, which contains what I quoted. It's followed by .TCL and .PRJ and .JID files, which don't seem to contain anything useful in the context. Unless it throws that report somewhere into a darkest corner of the harddrive, I don't see anything else.

Have you checked for licensing issues?

Maybe I don't know how but I haven't noticed anything about licensing. I can view the EULA (from 2012 - not so old) and nothing complains about licensing.


I don't know for sure, but Synplicity should need a license to run. I
seem to recall when my license expires I get an exit error of 2. Check
the Lattice web site to see what they say about licensing this tool.

--

Rick C

silverdr
Guest

Thu Jun 16, 2016 11:37 pm   



On Thursday, 16 June 2016 18:47:20 UTC+2, KJ wrote:
Quote:
Thanks! That's the only good news so far Smile So theoretically I should be
able to use the PAL output from Cypress Galaxy WARP (which is the only one
that produced something so far), somehow (yeah..) convert it into another
form of JEDEC file in a GAL format and then use to program all the GALs of
one main type I have (like all 16V8 in my case here), right?

I don't know that you can take the JEDEC file of one device and use it on a different one (i.e. 16R8 JEDEC file using on a 16V8). What I said was that you can take a JEDEC file and use it with any manufacturer's same device (i.e. Cypress 16V8 using on a Lattice 16V8).


That's what I mean. I have chips from different manufacturers but all are of the same type designation 16V8 and 20V8. But the only, theoretically possible path now is through Cypress tools, which generate some PAL type of JEDEC file. If I can convert it (somehow) to GAL16V8 type JEDEC file then this JEDEC file should work with all GAL16V8s I have, correct?

> Having said that though, it might be that you can take a 16R8 and use it to program a 16V8. When the GAL devices were first coming out in the 80s there were lots of manufacturers of SPLDs and competition. I wouldn't consider it to much of a stretch to think that Lattice V8 did accept a JEDEC file that originally was intended for an MMI 16R8 since it would allow them to grab market share even more easily. I just remember if that was the case or not. The parts are very similar after all.

Hm, interesting. Pardon my ignorance but what are the chances of damaging/"bricking" the chip when feeding the programmer with a wrong JEDEC file?

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