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FSM Design in verilog using iverilog.

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Jatin Sharma
Guest

Thu Dec 26, 2019 6:16 pm   



I am writing an FSM design example to detect sequence "0110". I have written the code but constantly getting syntax error afte the line always@(PS or x). Even if i remove the code after always@(PS,x) still i am getting the same error in the that line.

//////////////////code////////////////////////
module sequence_detector(x,clk,reset,z);
output reg z;
input clk,reset,x;

parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3;
reg[0:1] PS,NS;

always@(posedge clk or posedge reset)
begin
if(reset)
PS <= S0;
else
PS <= NS;
end
always@(PS,x)
begin
case (PS)
S0:
begin
z = 0;
NS = x ? S0 : S1;
end
S1:
begin
z = 0;
NS = x ? S2 : S1;
end
S2:
begin
z = 0;
NS = x ? S3 : S1;
end
S3:
begin
z = x ? 0 : 1;
NS = x ? S0 : S1;
end
default:
begin
z = 0;
NS = S0;
end
endcase
end
endmodule
//////////////////////////////////////////////////////////////////

/////////////////////////////error////////////////////////////////
seq_detector_tb.v:17: syntax error
seq_detector_tb.v:19: Syntax in assignment statement l-value.
seq_detector_tb.v:19: syntax error
seq_detector_tb.v:19: error: invalid module item.
seq_detector_tb.v:19: syntax error
seq_detector_tb.v:19: error: invalid module item.
seq_detector_tb.v:19: syntax error
seq_detector_tb.v:19: error: invalid module item.
seq_detector_tb.v:20: syntax error
seq_detector_tb.v:20: error: invalid module item.
seq_detector_tb.v:20: syntax error
seq_detector_tb.v:20: error: invalid module item.
seq_detector_tb.v:20: syntax error
seq_detector_tb.v:20: error: invalid module item.
seq_detector_tb.v:20: syntax error
seq_detector_tb.v:20: error: invalid module item.
seq_detector_tb.v:21: syntax error
seq_detector_tb.v:21: error: invalid module item.
seq_detector_tb.v:21: syntax error
seq_detector_tb.v:21: error: invalid module item.
seq_detector_tb.v:21: syntax error
seq_detector_tb.v:21: error: invalid module item.
seq_detector_tb.v:21: syntax error
seq_detector_tb.v:21: error: invalid module item.
seq_detector_tb.v:22: syntax error
seq_detector_tb.v:22: error: invalid module item.
seq_detector_tb.v:23: syntax error
I give up.

Rick C
Guest

Fri Dec 27, 2019 12:04 am   



On Thursday, December 26, 2019 at 11:16:37 AM UTC-5, Jatin Sharma wrote:
Quote:
I am writing an FSM design example to detect sequence "0110". I have written the code but constantly getting syntax error afte the line always@(PS or x). Even if i remove the code after always@(PS,x) still i am getting the same error in the that line.

//////////////////code////////////////////////
module sequence_detector(x,clk,reset,z);
output reg z;
input clk,reset,x;

parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3;
reg[0:1] PS,NS;

always@(posedge clk or posedge reset)
begin
if(reset)
PS <= S0;
else
PS <= NS;
end
always@(PS,x)
begin
case (PS)
S0:
begin
z = 0;
NS = x ? S0 : S1;
end
S1:
begin
z = 0;
NS = x ? S2 : S1;
end
S2:
begin
z = 0;
NS = x ? S3 : S1;
end
S3:
begin
z = x ? 0 : 1;
NS = x ? S0 : S1;
end
default:
begin
z = 0;
NS = S0;
end
endcase
end
endmodule
//////////////////////////////////////////////////////////////////

/////////////////////////////error////////////////////////////////
seq_detector_tb.v:17: syntax error
seq_detector_tb.v:19: Syntax in assignment statement l-value.
seq_detector_tb.v:19: syntax error
seq_detector_tb.v:19: error: invalid module item.
seq_detector_tb.v:19: syntax error
seq_detector_tb.v:19: error: invalid module item.
seq_detector_tb.v:19: syntax error
seq_detector_tb.v:19: error: invalid module item.
seq_detector_tb.v:20: syntax error
seq_detector_tb.v:20: error: invalid module item.
seq_detector_tb.v:20: syntax error
seq_detector_tb.v:20: error: invalid module item.
seq_detector_tb.v:20: syntax error
seq_detector_tb.v:20: error: invalid module item.
seq_detector_tb.v:20: syntax error
seq_detector_tb.v:20: error: invalid module item.
seq_detector_tb.v:21: syntax error
seq_detector_tb.v:21: error: invalid module item.
seq_detector_tb.v:21: syntax error
seq_detector_tb.v:21: error: invalid module item.
seq_detector_tb.v:21: syntax error
seq_detector_tb.v:21: error: invalid module item.
seq_detector_tb.v:21: syntax error
seq_detector_tb.v:21: error: invalid module item.
seq_detector_tb.v:22: syntax error
seq_detector_tb.v:22: error: invalid module item.
seq_detector_tb.v:23: syntax error
I give up.


I don't know Verilog, but looking at your code, I see you use

always@(posedge clk or posedge reset)

and the error is with

always@(PS,x)

Why does one line use "or" and the other line use a comma? Is one wrong?

--

Rick C.

- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209

Charlie
Guest

Fri Dec 27, 2019 2:34 am   



On 12/26/2019 11:16 AM, Jatin Sharma wrote:
Quote:
I am writing an FSM design example to detect sequence "0110". I have written the code but constantly getting syntax error afte the line always@(PS or x). Even if i remove the code after always@(PS,x) still i am getting the same error in the that line.

//////////////////code////////////////////////
module sequence_detector(x,clk,reset,z);
output reg z;
input clk,reset,x;

parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3;
reg[0:1] PS,NS;

always@(posedge clk or posedge reset)
begin
if(reset)
PS <= S0;
else
PS <= NS;
end
always@(PS,x)
begin
case (PS)
S0:
begin
z = 0;
NS = x ? S0 : S1;
end
S1:
begin
z = 0;
NS = x ? S2 : S1;
end
S2:
begin
z = 0;
NS = x ? S3 : S1;
end
S3:
begin
z = x ? 0 : 1;
NS = x ? S0 : S1;
end
default:
begin
z = 0;
NS = S0;
end
endcase
end
endmodule
//////////////////////////////////////////////////////////////////

/////////////////////////////error////////////////////////////////
seq_detector_tb.v:17: syntax error
seq_detector_tb.v:19: Syntax in assignment statement l-value.
seq_detector_tb.v:19: syntax error
seq_detector_tb.v:19: error: invalid module item.
seq_detector_tb.v:19: syntax error
seq_detector_tb.v:19: error: invalid module item.
seq_detector_tb.v:19: syntax error
seq_detector_tb.v:19: error: invalid module item.
seq_detector_tb.v:20: syntax error
seq_detector_tb.v:20: error: invalid module item.
seq_detector_tb.v:20: syntax error
seq_detector_tb.v:20: error: invalid module item.
seq_detector_tb.v:20: syntax error
seq_detector_tb.v:20: error: invalid module item.
seq_detector_tb.v:20: syntax error
seq_detector_tb.v:20: error: invalid module item.
seq_detector_tb.v:21: syntax error
seq_detector_tb.v:21: error: invalid module item.
seq_detector_tb.v:21: syntax error
seq_detector_tb.v:21: error: invalid module item.
seq_detector_tb.v:21: syntax error
seq_detector_tb.v:21: error: invalid module item.
seq_detector_tb.v:21: syntax error
seq_detector_tb.v:21: error: invalid module item.
seq_detector_tb.v:22: syntax error
seq_detector_tb.v:22: error: invalid module item.
seq_detector_tb.v:23: syntax error
I give up.


Your code compiles under Xilinx ISE without errors or warnings.

Charlie

Kevin Neilson
Guest

Fri Dec 27, 2019 9:29 pm   



On Thursday, December 26, 2019 at 9:16:37 AM UTC-7, Jatin Sharma wrote:
Quote:
I am writing an FSM design example to detect sequence "0110". I have written the code but constantly getting syntax error afte the line always@(PS or x). Even if i remove the code after always@(PS,x) still i am getting the same error in the that line.

//////////////////code////////////////////////
module sequence_detector(x,clk,reset,z);
output reg z;
input clk,reset,x;

parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3;
reg[0:1] PS,NS;

always@(posedge clk or posedge reset)
begin
if(reset)
PS <= S0;
else
PS <= NS;
end
always@(PS,x)
begin
case (PS)
S0:
begin
z = 0;
NS = x ? S0 : S1;
end
S1:
begin
z = 0;
NS = x ? S2 : S1;
end
S2:
begin
z = 0;
NS = x ? S3 : S1;
end
S3:
begin
z = x ? 0 : 1;
NS = x ? S0 : S1;
end
default:
begin
z = 0;
NS = S0;
end
endcase
end
endmodule
//////////////////////////////////////////////////////////////////

/////////////////////////////error////////////////////////////////
seq_detector_tb.v:17: syntax error
seq_detector_tb.v:19: Syntax in assignment statement l-value.
seq_detector_tb.v:19: syntax error
seq_detector_tb.v:19: error: invalid module item.
seq_detector_tb.v:19: syntax error
seq_detector_tb.v:19: error: invalid module item.
seq_detector_tb.v:19: syntax error
seq_detector_tb.v:19: error: invalid module item.
seq_detector_tb.v:20: syntax error
seq_detector_tb.v:20: error: invalid module item.
seq_detector_tb.v:20: syntax error
seq_detector_tb.v:20: error: invalid module item.
seq_detector_tb.v:20: syntax error
seq_detector_tb.v:20: error: invalid module item.
seq_detector_tb.v:20: syntax error
seq_detector_tb.v:20: error: invalid module item.
seq_detector_tb.v:21: syntax error
seq_detector_tb.v:21: error: invalid module item.
seq_detector_tb.v:21: syntax error
seq_detector_tb.v:21: error: invalid module item.
seq_detector_tb.v:21: syntax error
seq_detector_tb.v:21: error: invalid module item.
seq_detector_tb.v:21: syntax error
seq_detector_tb.v:21: error: invalid module item.
seq_detector_tb.v:22: syntax error
seq_detector_tb.v:22: error: invalid module item.
seq_detector_tb.v:23: syntax error
I give up.


The problem is probably here:

NS = x ? S0 : S1;

This should use the conditional operator:

NS == x ? S0 : S1;

The same goes for some lines where z is assigned.

Are you using a really old book to learn Verilog? The port list syntax you use is archaic and was obsoleted in Verilog-2001 or maybe 1995.

Kevin Neilson
Guest

Sat Dec 28, 2019 9:49 am   



Ignore my post. I was mistaken.

Gabor
Guest

Sun Dec 29, 2019 6:23 pm   



On Thursday, 12/26/2019 11:16 AM, Jatin Sharma wrote:
Quote:
I am writing an FSM design example to detect sequence "0110". I have written the code but constantly getting syntax error afte the line always@(PS or x). Even if i remove the code after always@(PS,x) still i am getting the same error in the that line.

//////////////////code////////////////////////
module sequence_detector(x,clk,reset,z);
output reg z;
input clk,reset,x;

parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3;
reg[0:1] PS,NS;

always@(posedge clk or posedge reset)
begin
if(reset)
PS <= S0;
else
PS <= NS;
end
always@(PS,x)
begin
case (PS)
S0:
begin
z = 0;
NS = x ? S0 : S1;
end
S1:
begin
z = 0;
NS = x ? S2 : S1;
end
S2:
begin
z = 0;
NS = x ? S3 : S1;
end
S3:
begin
z = x ? 0 : 1;
NS = x ? S0 : S1;
end
default:
begin
z = 0;
NS = S0;
end
endcase
end
endmodule
//////////////////////////////////////////////////////////////////

/////////////////////////////error////////////////////////////////
seq_detector_tb.v:17: syntax error
seq_detector_tb.v:19: Syntax in assignment statement l-value.
seq_detector_tb.v:19: syntax error
seq_detector_tb.v:19: error: invalid module item.
seq_detector_tb.v:19: syntax error
seq_detector_tb.v:19: error: invalid module item.
seq_detector_tb.v:19: syntax error
seq_detector_tb.v:19: error: invalid module item.
seq_detector_tb.v:20: syntax error
seq_detector_tb.v:20: error: invalid module item.
seq_detector_tb.v:20: syntax error
seq_detector_tb.v:20: error: invalid module item.
seq_detector_tb.v:20: syntax error
seq_detector_tb.v:20: error: invalid module item.
seq_detector_tb.v:20: syntax error
seq_detector_tb.v:20: error: invalid module item.
seq_detector_tb.v:21: syntax error
seq_detector_tb.v:21: error: invalid module item.
seq_detector_tb.v:21: syntax error
seq_detector_tb.v:21: error: invalid module item.
seq_detector_tb.v:21: syntax error
seq_detector_tb.v:21: error: invalid module item.
seq_detector_tb.v:21: syntax error
seq_detector_tb.v:21: error: invalid module item.
seq_detector_tb.v:22: syntax error
seq_detector_tb.v:22: error: invalid module item.
seq_detector_tb.v:23: syntax error
I give up.


Is "seq_detector_tb.v" the file containing the code you posted, or is it
a test bench that instantiates that code? The errors are all in that
file.

--
Gabor

elektroda.net NewsGroups Forum Index - Verilog Language - FSM Design in verilog using iverilog.

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