Gabor
Guest
Thu Jul 21, 2011 3:52 pm
Dustin Brothers wrote:
Quote:
I am wondering if have two FPGAs being programmed from the same EEPROM is even a valid JTAG structure? Someone please correct if I am incorrect and has designed a working system this way before. I would almost lean towards having the JTAG chain only be
EEPROM -> FPGA1
Then have FPGA1 read the bit stream out of EEPROM and program FPGA2. Therefore you don't have bus contention between the two FPGAs. FPGA2 is then like a ghost FPGA on the JTAG chain.
Does this seem logical? I have just never heard of one EEPROM being dedicated to two FPGAs before with identical bit files.
Actually it is quite common to use a single PROM or flash to program
multiple FPGA's. This connection scheme is shown in the Spartan 3
Generation Configuration User Guide.
From the other posts in the thread, it seems more likely to be a
problem with bit file generation rather than the board-level
connections.
-- Gabor
Dustin Brothers
Guest
Mon Jul 25, 2011 4:04 pm
Gabor,
Ok awesome, thanks for the clarity. I have never designed a system in this configuration which is why I was asking :)
-D
