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Guest

Mon Nov 13, 2017 9:47 pm   



Den mandag den 13. november 2017 kl. 17.49.15 UTC+1 skrev Rick C. Hodgin:
Quote:
On Monday, November 13, 2017 at 11:28:09 AM UTC-5, lasselangwad...@gmail.com wrote:
Den fredag den 10. november 2017 kl. 23.03.06 UTC+1 skrev Rick C. Hodgin:
then you should probably start with a basic verilog project with some blinking leds and not a giant hairball of a CISC cpu...

I've done that. I've made the KITT car red light thing. I've
responded to buttons. I've debounced inputs. An on Arduino,
which is basically C code, I've made tone generators, sent output
on a clock to a remote device on 18 pins, etc.

any of that in verilog?

Yes. Using Lattice's Diamond software on a Lattice XP2 Brevia board:


writing verilog or copy-pasting verilog ?

anyway, 99% of such a project will be done in a simulator

Rick C. Hodgin
Guest

Mon Nov 13, 2017 9:54 pm   



On Monday, November 13, 2017 at 2:47:48 PM UTC-5, lasselangwad...@gmail.com wrote:
Quote:
Den mandag den 13. november 2017 kl. 17.49.15 UTC+1 skrev Rick C. Hodgin:
On Monday, November 13, 2017 at 11:28:09 AM UTC-5, lasselangwad...@gmail.com wrote:
Den fredag den 10. november 2017 kl. 23.03.06 UTC+1 skrev Rick C. Hodgin:
then you should probably start with a basic verilog project with some blinking leds and not a giant hairball of a CISC cpu...

I've done that. I've made the KITT car red light thing. I've
responded to buttons. I've debounced inputs. An on Arduino,
which is basically C code, I've made tone generators, sent output
on a clock to a remote device on 18 pins, etc.

any of that in verilog?

Yes. Using Lattice's Diamond software on a Lattice XP2 Brevia board:

writing verilog or copy-pasting verilog ?


Writing Verilog. I've also written a CPU core that synthesized in
Altera's Quartus II software, but I never debugged it and I have no
idea if it actually works:

http://libsf.org:8990/projects/LIB/repos/libsf/browse/arxoda/oppie/oppie1/oppie1.v

http://libsf.org:8990/projects/LIB/repos/libsf/browse/arxoda/oppie/oppie1/debo-1-actual.png

http://libsf.org:8990/projects/LIB/repos/libsf/browse/arxoda/oppie/oppie-1.png

> anyway, 99% of such a project will be done in a simulator

That would be great. How do I do it? What tools are available for
the Alter Cyclone V GX Starter Kit toolset?

--
Rick C. Hodgin


Guest

Mon Nov 13, 2017 10:06 pm   



Den mandag den 13. november 2017 kl. 20.54.12 UTC+1 skrev Rick C. Hodgin:
Quote:
On Monday, November 13, 2017 at 2:47:48 PM UTC-5, lasselangwad...@gmail.com wrote:
Den mandag den 13. november 2017 kl. 17.49.15 UTC+1 skrev Rick C. Hodgin:
On Monday, November 13, 2017 at 11:28:09 AM UTC-5, lasselangwad...@gmail.com wrote:
Den fredag den 10. november 2017 kl. 23.03.06 UTC+1 skrev Rick C. Hodgin:
then you should probably start with a basic verilog project with some blinking leds and not a giant hairball of a CISC cpu...

I've done that. I've made the KITT car red light thing. I've
responded to buttons. I've debounced inputs. An on Arduino,
which is basically C code, I've made tone generators, sent output
on a clock to a remote device on 18 pins, etc.

any of that in verilog?

Yes. Using Lattice's Diamond software on a Lattice XP2 Brevia board:

writing verilog or copy-pasting verilog ?

Writing Verilog. I've also written a CPU core that synthesized in
Altera's Quartus II software, but I never debugged it and I have no
idea if it actually works:

http://libsf.org:8990/projects/LIB/repos/libsf/browse/arxoda/oppie/oppie1/oppie1.v

http://libsf.org:8990/projects/LIB/repos/libsf/browse/arxoda/oppie/oppie1/debo-1-actual.png

http://libsf.org:8990/projects/LIB/repos/libsf/browse/arxoda/oppie/oppie-1.png

anyway, 99% of such a project will be done in a simulator

That would be great. How do I do it? What tools are available for
the Alter Cyclone V GX Starter Kit toolset?


what's wrong with icarus iverilog? no point in looking at specific boards or fpgas until you have it working in a simulator

Rick C. Hodgin
Guest

Mon Nov 13, 2017 10:15 pm   



On Monday, November 13, 2017 at 3:06:44 PM UTC-5, lasselangwad...@gmail.com wrote:
Quote:
Den mandag den 13. november 2017 kl. 20.54.12 UTC+1 skrev Rick C. Hodgin:
On Monday, November 13, 2017 at 2:47:48 PM UTC-5, lasselangwad...@gmail.com wrote:
Den mandag den 13. november 2017 kl. 17.49.15 UTC+1 skrev Rick C. Hodgin:
writing verilog or copy-pasting verilog ?

Writing Verilog. I've also written a CPU core that synthesized in
Altera's Quartus II software, but I never debugged it and I have no
idea if it actually works:

http://libsf.org:8990/projects/LIB/repos/libsf/browse/arxoda/oppie/oppie1/oppie1.v

http://libsf.org:8990/projects/LIB/repos/libsf/browse/arxoda/oppie/oppie1/debo-1-actual.png

http://libsf.org:8990/projects/LIB/repos/libsf/browse/arxoda/oppie/oppie-1.png

anyway, 99% of such a project will be done in a simulator

That would be great. How do I do it? What tools are available for
the Alter Cyclone V GX Starter Kit toolset?

what's wrong with icarus iverilog? no point in looking at specific boards or fpgas until you have it working in a simulator


I've found the tools clunky. I want to see some kind of visualization
like this:

http://www.visual6502.org/JSSim/index.html

Which produces information on runtime like this:

http://www.visual6502.org/JSSim/expert.html

And produces some kind of output like this:

(click the "Trace More" button many times)

-----
The reason I stopped working in Verilog was because I found it textual
and confusing. I had intended to write my Logician tool, which would
be a Blender node-like arrangement of hardware, allowing me to sample
all data lines, and visualize it as with the 6502 visualization.

Blender Node Editor (at 1:18 and after):
https://www.youtube.com/watch?v=sc-ptGft9Vk&t=1m18s

I haven't had time to do it yet, but there must be some tool closer
to that out there. If not, that's where we should start (writing
that tool for people to use).

--
Rick C. Hodgin

Rick C. Hodgin
Guest

Tue Dec 12, 2017 10:10 pm   



On Friday, November 10, 2017 at 10:35:44 AM UTC-5, Rick C. Hodgin wrote:
Quote:
The 80386DX CPU had 132 pins:

80386DX and 80386SX pinouts:
http://www.rfwireless-world.com/images/80386-pin-diagram.jpg
https://image.slidesharecdn.com/salientfeatursof80386-140822084001-phpapp02/95/salient-featurs-of-80386-14-638.jpg?cb=1408709884

General architecture:
http://www.nptel.ac.in/courses/Webcourse-contents/IISc-BANG/Microprocessors%20and%20Microcontrollers/pdf/Teacher_Slides/mod8/M8L1.pdf

Of these pins on the DX variant:

32 pins -- data
30 pins -- address
4 pins -- byte enables in 32-bit writes
1 pin -- Read/write
1 pin -- Data/Control
1 pin -- Memory/IO
1 pin -- Bus mastering lock issued by CPU
1 pin -- Bus16 size (16-bit when asserted, normally 32-bit)
1 pin -- Next address (for pipelining)
1 pin -- Address valid signal
--
73 pins -- For basic I/O

3 pins -- Math-coprocessor support
1 pin -- Ready (or Wait, for bus cycles to complete)
2 pins -- Hold and Hold Acknowledge (for bus mastering)
2 pins -- Interrupt and Non-masktable Interrupt
--
8 pins -- General coordination with external peripherals

1 pin -- Reset
1 pin -- Double-pumped clock
--
2 pins -- System input

The rest of the pins are unused, go to VSS or VCC. This means that for a
full 80386 "motherboard" only 83 pins are required to fully support its
operation, 67 of which are address, data, and data type, leaving really
only 15 pins of complex operation for a state machine.

-----
Would anybody be able to help me create this 80386 motherboard using an
AMD Am386 CPU, which is a static CPU operating from 0 to 40 MHz? I would
like to get it working with a single-step operation for design validation,
and then to begin ramping it up.

I figure I'll have an area of ROM which the CPU boots to load, which is a
tiny real mode program, which begins computing something that can be exam-
ined by the FPGA to test successful operation. And then move on to more
complex operations, including a custom microkernel.


Now that the intrusion appears to be over, would anybody like to help me
in preparation for this project?

Specifically, I'd like some help in guiding me toward the type of board
and sockets I'll need. I think I know what to do, but without someone
to say "yay" or "nay" I'm just guessing.

It will need a 132-pin PGA, a custom board which connects into the
three parallel 40-pin adapter board I have for my FPGA. In that way,
the 80386 chip will ride right above the FPGA, with traversing the main
40-pin-to-FPGA connection, and the 80386 board-to-40-pin connection.

80386
=========
|||||||||
===========================
|| || || <=== 3x 40-pin
=======================
|||| <=== Proprietary 120+pin adapter
=====[ FPGA ]==================

The FPGA I have is about 6" square, with the adapter board being about
2" x 3". The custom board I'll build will be about 3" x 3". The total
distance from FPGA to CPU will be about 9".

The Am386 CPU I plan to use is a static part able to run between 0 MHz
and 40 MHz inclusive. I plan to run around 1 MHz to start.

Please offer any advice. Thank you.

--
Rick C. Hodgin

Rick C. Hodgin
Guest

Thu Dec 14, 2017 4:29 pm   



On Tuesday, December 12, 2017 at 3:11:01 PM UTC-5, Rick C. Hodgin wrote:
Quote:
It will need a 132-pin PGA, a custom board which connects into the
three parallel 40-pin adapter board I have for my FPGA. In that way,
the 80386 chip will ride right above the FPGA, with traversing the main
40-pin-to-FPGA connection, and the 80386 board-to-40-pin connection.

80386
=========
|||||||||
===========================
|| || || <=== 3x 40-pin
=======================
|||| <=== Proprietary 120+pin adapter
=====[ FPGA ]==================


I had the thought I can build it this way to have a one-sided board:

====================================
||||||| || || || <=== 3x 40-pin
80386 =======================
|||| <=== Proprietary 120+pin adapter
=====[ FPGA ]==================

And I may be able to build it this way:

=======================
|||| |||||||
=====[ FPGA ]================== 80386

Where the 80386 plugs directly into the proprietary 120+pin adapter.

This would give me a framework where I can create the custom board
to use the appropriate GPIO pins, and +3.3 and GND pins, to provide
power to the CPU. My goal then is to generate the double-pumped
clock at 2 MHz, and respond to the bus signals with a state machine,
and provide a memory controller for the actual instructions.

Will anybody help me?

--
Rick C. Hodgin

Rick C. Hodgin
Guest

Wed Dec 20, 2017 3:49 pm   



On Monday, November 13, 2017 at 3:06:44 PM UTC-5, lasselangwad...@gmail.com wrote:
Quote:
Den mandag den 13. november 2017 kl. 20.54.12 UTC+1 skrev Rick C. Hodgin:
On Monday, November 13, 2017 at 2:47:48 PM UTC-5, lasselangwad...@gmail.com wrote:
Den mandag den 13. november 2017 kl. 17.49.15 UTC+1 skrev Rick C. Hodgin:
On Monday, November 13, 2017 at 11:28:09 AM UTC-5, lasselangwad...@gmail.com wrote:
Den fredag den 10. november 2017 kl. 23.03.06 UTC+1 skrev Rick C. Hodgin:
then you should probably start with a basic verilog project with some blinking leds and not a giant hairball of a CISC cpu...

I've done that. I've made the KITT car red light thing. I've
responded to buttons. I've debounced inputs. An on Arduino,
which is basically C code, I've made tone generators, sent output
on a clock to a remote device on 18 pins, etc.

any of that in verilog?

Yes. Using Lattice's Diamond software on a Lattice XP2 Brevia board:

writing verilog or copy-pasting verilog ?

Writing Verilog. I've also written a CPU core that synthesized in
Altera's Quartus II software, but I never debugged it and I have no
idea if it actually works:

http://libsf.org:8990/projects/LIB/repos/libsf/browse/arxoda/oppie/oppie1/oppie1.v

http://libsf.org:8990/projects/LIB/repos/libsf/browse/arxoda/oppie/oppie1/debo-1-actual.png

http://libsf.org:8990/projects/LIB/repos/libsf/browse/arxoda/oppie/oppie-1.png

anyway, 99% of such a project will be done in a simulator

That would be great. How do I do it? What tools are available for
the Alter Cyclone V GX Starter Kit toolset?

what's wrong with icarus iverilog? no point in looking at specific boards or fpgas until you have it working in a simulator


How would I get a project like this working in simulation first? I'm
going to be reading real input from another piece of hardware. I'll
be giving it a clock signal, and responding to events based on whatever
it's doing.

About the only real ability I have to control the CPU is in the clock
signal, which I should be able to step as needed on the Am386 part,
which is static.

Would I build a state machine and give it sample inputs and make sure
it's all working? What if the state machine I build does not match
what I find in the real-world Am386 hardware protocols?

I'm expecting to find a lot of things it does that are non-standard.
I am expecting to be able to capture and code for each of them one-
by-one, with the bulk of the design being as predicted.

--
Rick C. Hodgin

Rick C. Hodgin
Guest

Thu Dec 21, 2017 11:33 am   



On Monday, November 13, 2017 at 3:15:12 PM UTC-5, Rick C. Hodgin wrote:
Quote:
On Monday, November 13, 2017 at 3:06:44 PM UTC-5, lasselangwad...@gmail.com wrote:
what's wrong with icarus iverilog? no point in looking at specific boards or fpgas until you have it working in a simulator

I've found the tools clunky. I want to see some kind of visualization
like this:

http://www.visual6502.org/JSSim/index.html

Which produces information on runtime like this:

http://www.visual6502.org/JSSim/expert.html

And produces some kind of output like this:

(click the "Trace More" button many times)

-----
The reason I stopped working in Verilog was because I found it textual
and confusing. I had intended to write my Logician tool, which would
be a Blender node-like arrangement of hardware, allowing me to sample
all data lines, and visualize it as with the 6502 visualization.

Blender Node Editor (at 1:18 and after):
https://www.youtube.com/watch?v=sc-ptGft9Vk&t=1m18s

I haven't had time to do it yet, but there must be some tool closer
to that out there. If not, that's where we should start (writing
that tool for people to use).


I came across this toolset from ARM recently.

This is almost exactly what I envisioned Logician's interface
looking like at 2:15:
https://www.youtube.com/watch?v=n9cUiEdqdJU&t=2m15s

Specifically here at 2:36:
https://www.youtube.com/watch?v=n9cUiEdqdJU&t=2m36s

The drag-and-drop / "connect noodles" approach is what I
envisioned from Blender. So, this tool has almost exactly
what I'm looking for.

Except ... I do not like seeing outputs like these at 1:32:
https://www.youtube.com/watch?v=n9cUiEdqdJU&t=1m32s

The idea is: I work in direct models of hardware units, and
the tool generates the required source code for me.

--
Rick C. Hodgin

Richard Damon
Guest

Sat Dec 23, 2017 2:23 am   



On 12/21/17 4:33 AM, Rick C. Hodgin wrote:
Quote:
On Monday, November 13, 2017 at 3:15:12 PM UTC-5, Rick C. Hodgin wrote:
On Monday, November 13, 2017 at 3:06:44 PM UTC-5, lasselangwad...@gmail.com wrote:
what's wrong with icarus iverilog? no point in looking at specific boards or fpgas until you have it working in a simulator

I've found the tools clunky. I want to see some kind of visualization
like this:

http://www.visual6502.org/JSSim/index.html

Which produces information on runtime like this:

http://www.visual6502.org/JSSim/expert.html

And produces some kind of output like this:

(click the "Trace More" button many times)

-----
The reason I stopped working in Verilog was because I found it textual
and confusing. I had intended to write my Logician tool, which would
be a Blender node-like arrangement of hardware, allowing me to sample
all data lines, and visualize it as with the 6502 visualization.

Blender Node Editor (at 1:18 and after):
https://www.youtube.com/watch?v=sc-ptGft9Vk&t=1m18s

I haven't had time to do it yet, but there must be some tool closer
to that out there. If not, that's where we should start (writing
that tool for people to use).

I came across this toolset from ARM recently.


The Tool in the video is NOT from ARM, but is the Xilinx FPGA tool, and
since some of their FPGAs include a hard core embedded ARM (actually 2),
and others can create cores within the fabric, the tool provides a good
environment for building systems around ARM cores, so you cal learn the
protocols in the cores. There are also a number of peripheral cores
provided to interface with the processor core provided.

Most of the major FPGA manufactures (at least those with FPGAs big
enough to have a processor core) have similar pieces in their tools.
Quote:

This is almost exactly what I envisioned Logician's interface
looking like at 2:15:
https://www.youtube.com/watch?v=n9cUiEdqdJU&t=2m15s

Specifically here at 2:36:
https://www.youtube.com/watch?v=n9cUiEdqdJU&t=2m36s

The drag-and-drop / "connect noodles" approach is what I
envisioned from Blender. So, this tool has almost exactly
what I'm looking for.

Except ... I do not like seeing outputs like these at 1:32:
https://www.youtube.com/watch?v=n9cUiEdqdJU&t=1m32s


How else do you want to present the state of signals changing over time?
Quote:

The idea is: I work in direct models of hardware units, and
the tool generates the required source code for me.


This sort of interface has been around for what, maybe 30 years or more
(I used a similar graphical interface in the mid 80's for designing
parts of FPGAs).

These tools generally allow you to mix representations over layers, a
block in the graphical form can underneath be another graphical sheet,
or a textual module. And textual module can reference other textual
modules or graphical modules (actually, under the hood, the system
parses the graphical design and creates a textual module that get passed
to the synthesis program).

Rick C. Hodgin
Guest

Mon Dec 25, 2017 12:04 am   



On Friday, December 22, 2017 at 7:23:27 PM UTC-5, Richard Damon wrote:
Quote:
On 12/21/17 4:33 AM, Rick C. Hodgin wrote:
I came across this toolset from ARM recently.

The Tool in the video is NOT from ARM, but is the Xilinx FPGA tool, and
since some of their FPGAs include a hard core embedded ARM (actually 2),
and others can create cores within the fabric, the tool provides a good
environment for building systems around ARM cores, so you cal learn the
protocols in the cores. There are also a number of peripheral cores
provided to interface with the processor core provided.

Most of the major FPGA manufactures (at least those with FPGAs big
enough to have a processor core) have similar pieces in their tools.


I saw it on the ARM video linked below. My apologies for mis-ascribing
it. It's part of their ARM Education Media program. I have never used
Xilinx FPGAs. Only Lattice and .

Quote:
This is almost exactly what I envisioned Logician's interface
looking like at 2:15:
https://www.youtube.com/watch?v=n9cUiEdqdJU&t=2m15s

Specifically here at 2:36:
https://www.youtube.com/watch?v=n9cUiEdqdJU&t=2m36s

The drag-and-drop / "connect noodles" approach is what I
envisioned from Blender. So, this tool has almost exactly
what I'm looking for.

Except ... I do not like seeing outputs like these at 1:32:
https://www.youtube.com/watch?v=n9cUiEdqdJU&t=1m32s

How else do you want to present the state of signals changing over
time?


As in the 6502 simulation, with the ability to then graph the outputs in
the standard form, but I want to see things by value, by logical port,
by time, by change.

Quote:
The idea is: I work in direct models of hardware units, and
the tool generates the required source code for me.


This sort of interface has been around for what, maybe 30 years or more
(I used a similar graphical interface in the mid 80's for designing
parts of FPGAs).

These tools generally allow you to mix representations over layers, a
block in the graphical form can underneath be another graphical sheet,
or a textual module. And textual module can reference other textual
modules or graphical modules (actually, under the hood, the system
parses the graphical design and creates a textual module that get passed
to the synthesis program).


I have seen a couple in the Quartus tool and Lattice has something
that is GUI-based, but they are not quite on the same level of use as
the one show in the ARM video.

I may be reading more into the ARM video presentation than actually
exists as I have had a vision in my mind of what I want Logician to
look like, and may be projecting that vision onto the Xilinx tools.

--
Rick C. Hodgin

Rick C. Hodgin
Guest

Thu Dec 28, 2017 5:32 pm   



On Friday, November 10, 2017 at 10:35:44 AM UTC-5, Rick C. Hodgin wrote:
Quote:
The 80386DX CPU had 132 pins:

80386DX and 80386SX pinouts:
http://www.rfwireless-world.com/images/80386-pin-diagram.jpg
https://image.slidesharecdn.com/salientfeatursof80386-140822084001-phpapp02/95/salient-featurs-of-80386-14-638.jpg?cb=1408709884

General architecture:
http://www.nptel.ac.in/courses/Webcourse-contents/IISc-BANG/Microprocessors%20and%20Microcontrollers/pdf/Teacher_Slides/mod8/M8L1.pdf

Of these pins on the DX variant:

32 pins -- data
30 pins -- address
4 pins -- byte enables in 32-bit writes
1 pin -- Read/write
1 pin -- Data/Control
1 pin -- Memory/IO
1 pin -- Bus mastering lock issued by CPU
1 pin -- Bus16 size (16-bit when asserted, normally 32-bit)
1 pin -- Next address (for pipelining)
1 pin -- Address valid signal
--
73 pins -- For basic I/O

3 pins -- Math-coprocessor support
1 pin -- Ready (or Wait, for bus cycles to complete)
2 pins -- Hold and Hold Acknowledge (for bus mastering)
2 pins -- Interrupt and Non-masktable Interrupt
--
8 pins -- General coordination with external peripherals

1 pin -- Reset
1 pin -- Double-pumped clock
--
2 pins -- System input

The rest of the pins are unused, go to VSS or VCC. This means that for a
full 80386 "motherboard" only 83 pins are required to fully support its
operation, 67 of which are address, data, and data type, leaving really
only 15 pins of complex operation for a state machine.

-----
Would anybody be able to help me create this 80386 motherboard using an
AMD Am386 CPU, which is a static CPU operating from 0 to 40 MHz? I would
like to get it working with a single-step operation for design validation,
and then to begin ramping it up.

I figure I'll have an area of ROM which the CPU boots to load, which is a
tiny real mode program, which begins computing something that can be exam-
ined by the FPGA to test successful operation. And then move on to more
complex operations, including a custom microkernel.


What is a reliable provider for me to download design tools and make
this board? And are there providers that can do the soldering for me
as part of the price?

--
Rick C. Hodgin

Rick C. Hodgin
Guest

Sat Dec 30, 2017 7:54 pm   



On Thursday, December 28, 2017 at 10:32:09 AM UTC-5, Rick C. Hodgin wrote:
Quote:
What is a reliable provider for me to download design tools and make
this board? And are there providers that can do the soldering for me
as part of the price?


Does anybody have any advice? If not here, where should I go to get
information about custom boards designed to use with my Altera FPGA?

--
Rick C. Hodgin

Richard Damon
Guest

Sat Dec 30, 2017 10:18 pm   



On 12/30/17 12:54 PM, Rick C. Hodgin wrote:
Quote:
On Thursday, December 28, 2017 at 10:32:09 AM UTC-5, Rick C. Hodgin wrote:
What is a reliable provider for me to download design tools and make
this board? And are there providers that can do the soldering for me
as part of the price?

Does anybody have any advice? If not here, where should I go to get
information about custom boards designed to use with my Altera FPGA?

I am sure there are numerous 'maker' sites that could help you get
tools, designed, fabricate, and assemble such a board. I can't recommend
any in particular, as that isn't the sort of service I use, as I tend to
use higher level boards and larger volumes, so my providers aren't as
cost effective as they could be for your make one project.

Rick C. Hodgin
Guest

Sun Dec 31, 2017 10:20 am   



On Saturday, December 30, 2017 at 3:18:36 PM UTC-5, Richard Damon wrote:
Quote:
On 12/30/17 12:54 PM, Rick C. Hodgin wrote:
On Thursday, December 28, 2017 at 10:32:09 AM UTC-5, Rick C. Hodgin wrote:
What is a reliable provider for me to download design tools and make
this board? And are there providers that can do the soldering for me
as part of the price?

Does anybody have any advice? If not here, where should I go to get
information about custom boards designed to use with my Altera FPGA?

I am sure there are numerous 'maker' sites that could help you get
tools, designed, fabricate, and assemble such a board. I can't recommend
any in particular, as that isn't the sort of service I use, as I tend to
use higher level boards and larger volumes, so my providers aren't as
cost effective as they could be for your make one project.


I will try this company:

https://www.expresspcb.com

--
Rick C. Hodgin

Emilian Miron
Guest

Sun Dec 31, 2017 5:20 pm   



I've had very good experiences using Oshpark:
https://oshpark.com/

Also, the newest Kicad is very good with push&shove routing.

On Sunday, December 31, 2017 at 3:20:12 AM UTC-5, Rick C. Hodgin wrote:
Quote:
On Saturday, December 30, 2017 at 3:18:36 PM UTC-5, Richard Damon wrote:
On 12/30/17 12:54 PM, Rick C. Hodgin wrote:
On Thursday, December 28, 2017 at 10:32:09 AM UTC-5, Rick C. Hodgin wrote:
What is a reliable provider for me to download design tools and make
this board? And are there providers that can do the soldering for me
as part of the price?

Does anybody have any advice? If not here, where should I go to get
information about custom boards designed to use with my Altera FPGA?

I am sure there are numerous 'maker' sites that could help you get
tools, designed, fabricate, and assemble such a board. I can't recommend
any in particular, as that isn't the sort of service I use, as I tend to
use higher level boards and larger volumes, so my providers aren't as
cost effective as they could be for your make one project.

I will try this company:

https://www.expresspcb.com

--
Rick C. Hodgin


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