elektroda.net NewsGroups Forum Index - FPGA
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| Spartan3AN DDR2 - bad writing zeros | lusch | 2 / 0 | Wed Mar 10, 2010 1:59 am lusch |
using an FPGA to emulate a vintage computer [  Goto page: 1 ... 14, 15, 16 ] | Eric Chomko | 238 / 66 | Tue Mar 09, 2010 11:59 pm Michael Wojcik |
| Some Active-HDL questions | Pete Fraser | 7 / 1 | Tue Mar 09, 2010 10:11 pm rickman |
| Tabula. (FPGA start up) [ Goto page: 1, 2 ] | Symon | 22 / 4 | Tue Mar 09, 2010 7:30 pm Symon |
| Using the SignalTap Logic Analyzer | pinkisntwell | 1 / 1 | Mon Mar 08, 2010 7:34 pm fpgabuilder |
| Looking for a USB JTAG cable | Jason Thibodeau | 2 / 2 | Mon Mar 08, 2010 5:17 am GrizzlySteve |
| Laptop for FPGA design? [ Goto page: 1, 2 ] | Pete Fraser | 22 / 7 | Sun Mar 07, 2010 6:03 pm General Schvantzkoph |
| Virtex-4 driving a 5V CMOS | fpgauser | 6 / 21 | Sun Mar 07, 2010 3:56 pm ajv |
| Question in verilog testbench | Frank | 3 / 1 | Sun Mar 07, 2010 3:43 pm Frank |
| Spartan 3 minimum clock pulse width | Andrew Holme | 1 / 1 | Sun Mar 07, 2010 3:13 pm Nico Coesel |
| Actel is now the only FPGA vendor with hard-core processor i | Antti | 7 / 4 | Sun Mar 07, 2010 7:12 am radarman |
| FSM in BlockRAM | de4 | 13 / 3 | Sun Mar 07, 2010 2:09 am -jg |
| Ethernet development kit | Kastil Jan | 4 / 3 | Sat Mar 06, 2010 5:20 pm John Adair |
| Announce: 1 Pin Interface - FPGA and HW debug tool [ Goto page: 1, 2 ] | Nial Stewart | 16 / 8 | Fri Mar 05, 2010 10:37 am Nial Stewart |
| Place and Route | Jason Thibodeau | 5 / 5 | Thu Mar 04, 2010 10:20 pm Jason Thibodeau |
| EDK : FSL macros defined by Xilinx are wrong [ Goto page: 1 ... 322, 323, 324 ] | server | 4854 / 4808 | Thu Mar 04, 2010 10:10 pm Andy Peters |
| FPGA platform?? | JuNNi | 12 / 8 | Thu Mar 04, 2010 9:14 pm d_s_klein |
| Antti.... | Nial Stewart | 1 / 4 | Thu Mar 04, 2010 8:54 pm Antti |
| Using bidirectional pins in Verilog | Giorgos Tzampanakis | 1 / 2 | Wed Mar 03, 2010 10:17 pm Gabor |
| Xilinx IOBUF - operation Q (virtex4 chip) | Hunter | 2 / 4 | Wed Mar 03, 2010 10:03 pm Ed McGettigan |
| Spice simulation of IBIS details - model examples | -jg | 11 / 5 | Tue Mar 02, 2010 9:25 pm -jg |
| Frustration with Vendors! [ Goto page: 1, 2, 3, 4 ] | rickman | 52 / 13 | Tue Mar 02, 2010 11:21 am Kim Enkovaara |
| Derived clock violation in Virtex4 | Verictor | 10 / 9 | Sun Feb 28, 2010 2:08 am Jim Wu |
| FPGA Editor - Post Route Simulation after changes in Ncd fil | Charles | 2 / 10 | Sat Feb 27, 2010 7:15 pm Jim Wu |
| Altera data sheets. | Symon | 13 / 6 | Sat Feb 27, 2010 3:22 pm David Brown |
| What is the most area efficient CRC method | dlopez | 6 / 8 | Sat Feb 27, 2010 3:03 pm coffee_bender |
| Quartus - How to get a vector waveform file longer than 1000 | Giorgos Tzampanakis | 1 / 5 | Sat Feb 27, 2010 5:28 am Giorgos Tzampanakis |
| antti alive message | Antti | 2 / 7 | Fri Feb 26, 2010 7:59 am Antti |
| EDK spi ip core | lakshmi3489 | 5 / 5 | Fri Feb 26, 2010 5:46 am johnp |
| Xilinx XPS crash on Linux | pes | 1 / 5 | Thu Feb 25, 2010 9:00 pm Alan Fitch |
| Scrubbing in Virtex-4 | xabi | 1 / 5 | Thu Feb 25, 2010 4:12 pm he |
| Xilinx iodelay | Chris Maryan | 1 / 5 | Thu Feb 25, 2010 12:41 am John McCaskill |
| data2mem and rodata/data (Xilinx) | n5ac | 2 / 6 | Wed Feb 24, 2010 6:24 pm n5ac |
| Data2Mem ? BlockRAM ? Init BMM and MEM | de4 | 10 / 15 | Tue Feb 23, 2010 9:40 pm n5ac |
| Triming timing constraints from pin ... | Dek | 2 / 7 | Tue Feb 23, 2010 4:20 pm Dek |
| System design in FPGA [ Goto page: 1, 2 ] | jozamm | 16 / 14 | Tue Feb 23, 2010 3:47 pm jc |
| Reading UDP with FPGA | Dek | 9 / 12 | Tue Feb 23, 2010 7:06 am whygee |
| rocketio TX delay between sata0 and sata1 | msegura | 13 / 7 | Tue Feb 23, 2010 4:34 am Ed McGettigan |
| Looking for Ultimate RISC/MISC that runs LINUX Website | Derek Simmons | 2 / 7 | Tue Feb 23, 2010 2:19 am jacko |
| Quartus II IDE freezing on Arch 64 | bizarrefish | 3 / 8 | Mon Feb 22, 2010 4:06 pm Anssi Saari |
| how to read bmp file in vhdl | suni | 2 / 9 | Mon Feb 22, 2010 12:20 pm Martin Thompson |
| EDK 11,1 on Windows 7, 32 Bit | Antti | 7 / 7 | Mon Feb 22, 2010 11:36 am Maik H. |
| State machines in Quartus | Giorgos Tzampanakis | 2 / 8 | Sun Feb 21, 2010 10:57 pm Derek Simmons |
| BRAM16 error | bh.ines1806@gmail.com | 6 / 12 | Sun Feb 21, 2010 1:37 pm Anssi Saari |
| Unpredictable design [ Goto page: 1, 2 ] | de4 | 16 / 13 | Sun Feb 21, 2010 3:33 am rickman |
| what is incorrect about my usage of array with port entity? | brianwfarmer | 1 / 7 | Wed Feb 17, 2010 5:10 pm RCIngham |
| Board layout for FPGA [ Goto page: 1 ... 3, 4, 5 ] | TSMGrizzly | 68 / 42 | Wed Feb 17, 2010 8:04 am rickman |
| Differential Signaling Buffer | lakshmi3489 | 1 / 9 | Tue Feb 16, 2010 11:57 am lakshmi3489 |
| optimal no of inputs to be given in a test bench | chaitanyakurmala@gmail.co | 6 / 6 | Mon Feb 15, 2010 11:44 pm glen herrmannsfeldt |
| To get higher clock frequencies at output using propagation | Pallavi | 10 / 7 | Mon Feb 15, 2010 11:18 pm glen herrmannsfeldt |
