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Looking for a decent FPGA board with multiple Xilinx Virtex

maverick

1 / 20

Fri Nov 18, 2011 7:27 am maverick

ASIC design job vs FPGA design job

googler

14 / 24

Wed Nov 16, 2011 3:38 pm Jon Beniston

PCI Express development board [ Goto page: 1, 2 ]

zsolt.garamvolgyi

19 / 48

Wed Nov 16, 2011 7:46 am scrts

Enterpoint New Boards

John Adair

3 / 29

Mon Nov 14, 2011 5:29 pm John Adair

Fundamental DSP/speech processing patent for sale [ Goto page: 1, 2 ]

Dude Whocares

21 / 35

Wed Nov 09, 2011 5:16 pm fatalist

Choose between Cyclone II and Spartan II

Everett

2 / 32

Sat Nov 05, 2011 10:14 pm Michael S

PCI core with expansion ROM support

fpgaiua

3 / 42

Fri Nov 04, 2011 2:56 pm peio

draw lines, circles, squares on FPGA by mouse and display on

lexuancong

4 / 68

Fri Nov 04, 2011 12:51 am Frank Buss

Xilinx USB II Cable driver under Gentoo Linux

Petter Gustad

4 / 26

Thu Nov 03, 2011 3:26 pm Petter Gustad

CSV pinout from Actel

self

1 / 26

Thu Nov 03, 2011 12:18 pm Thomas Stanka

FPGA development [ Goto page: 1, 2 ]

thunder

17 / 61

Sat Oct 29, 2011 8:52 pm glen herrmannsfeldt

Clock Phase Fun on Cyclone III

Rob Gaddi

1 / 29

Thu Oct 27, 2011 2:03 pm KJ

Peter Alfke has passed away [ Goto page: 1, 2 ]

Suhaib Fahmy

19 / 72

Wed Oct 26, 2011 8:16 pm Frank Buss

Modelsim on windoz save settings in a file rather than regis

dgreig

2 / 22

Wed Oct 26, 2011 7:05 pm dgreig

newable need help

Guest

1 / 21

Wed Oct 26, 2011 1:45 pm RCIngham

FPGA functional flow..please help!

vibha

2 / 26

Wed Oct 26, 2011 7:58 am backhus

ADC by using counter method on FPGA using VHDL language

VIJAY KUMAR

2 / 31

Wed Oct 26, 2011 7:47 am backhus

Spartan changes in glitch sensitivity [ Goto page: 1, 2 ]

Jon Elson

16 / 40

Tue Oct 25, 2011 7:56 pm Jon Elson

Reference books on microprocessor design with VHDL

VIJAY KUMAR

1 / 30

Tue Oct 25, 2011 8:42 am RCIngham

wireless module for DSP stratix III

sato

1 / 23

Sun Oct 23, 2011 11:50 pm wzab

Doulos training courses at Xilinx

Mr.CRC

9 / 47

Sun Oct 23, 2011 7:18 pm Jonathan Bromley

USB hangs on the Xilinx USB II Cable

General Schvantzkoph

2 / 21

Wed Oct 19, 2011 8:55 pm General Schvantzkoph

Xilinx EDK: XPS netlist combination error

Finn S. Nielsen

2 / 50

Wed Oct 19, 2011 12:27 am Finn S. Nielsen

Synthesizable heap-sorter for FPGA - BSD licensed sources

wzab

1 / 30

Fri Oct 14, 2011 3:10 pm Wojtek Zabołotny

Microblaze Resources such as BRAMS, LUTS

hrishi24h

2 / 36

Wed Oct 12, 2011 7:41 am Martin Thompson

high speed place and route about xilinx

bjzhangwn@gmail.com

3 / 32

Mon Oct 10, 2011 6:38 pm Guest

MAXDELAY constraint

Andrew Holme

7 / 64

Sun Oct 09, 2011 2:19 pm Guy Eschemann

VHDL connection problem

maxascent

3 / 35

Thu Oct 06, 2011 11:58 am Thomas Stanka

Testbench

maxascent

4 / 33

Wed Oct 05, 2011 1:03 pm Brian Drummond

macro

molka

2 / 33

Wed Oct 05, 2011 9:02 am backhus

FPGA acceleration v.s. GPU acceleration

vcar

6 / 60

Tue Oct 04, 2011 8:11 pm glen herrmannsfeldt

most stable version of ISE ?

Mike Harrison

3 / 30

Mon Oct 03, 2011 5:51 pm Gabor

VHDL problem

maxascent

4 / 31

Mon Oct 03, 2011 2:16 pm maxascent

How do they handle shorts during the dynamic reconfiguration

valtih1978

6 / 68

Mon Oct 03, 2011 11:49 am Guest

Xilinx SP605 DDR3 Allegro 15.7 Viewer Questions

Brad Smallridge

5 / 50

Mon Oct 03, 2011 1:29 am Brian Davis

Implementation Issue

James

3 / 37

Tue Sep 27, 2011 12:58 pm RCIngham

comparing Xilinx XC3S500E-4CPG132C vs Altera Cyclone IV FPG

jleslie48

8 / 42

Mon Sep 26, 2011 9:12 pm glen herrmannsfeldt

FPGA + TVP70025i Board

Test01

2 / 46

Mon Sep 26, 2011 10:22 am scrts

Modelsim cannot run its example tcl

fl

2 / 37

Mon Sep 26, 2011 7:27 am HT-Lab

Registers at I/O

valtih1978

7 / 33

Sun Sep 25, 2011 5:57 pm Mike Treseler

Xilinx Spartan-3 Starter Kit and Webpack 13.2

alekceywk

2 / 60

Thu Sep 22, 2011 7:41 am backhus

Hiring Engineers Colorado

Gaile Meeks

2 / 35

Thu Sep 22, 2011 12:14 am Dustin

SIM card 1.8V / 3V sensing

Mike Perkins

2 / 42

Tue Sep 20, 2011 11:26 am Brian Drummond

Virtex 6 dev. board suppliers?

rupertlssmith@googlemail.

6 / 39

Mon Sep 19, 2011 8:11 pm Ed McGettigan

Has anybody used IOB_DLY_ADJ with S(2:0) input?

Svenn Are Bjerkem

1 / 33

Mon Sep 19, 2011 3:29 pm Svenn Are Bjerkem

How to digitize the VGA output using FPGA?

Test01

5 / 37

Mon Sep 19, 2011 8:02 am Morten Leikvoll

clock enable for fixed interval

Jim

7 / 31

Mon Sep 19, 2011 7:48 am backhus

LFSR in xilinx 13.2

salimbaba

4 / 32

Fri Sep 16, 2011 2:35 pm FPGA ACE, LLC

reduce EDK synthesis time

catto

4 / 44

Thu Sep 15, 2011 3:26 pm fpga_me

CONSTRAINTS

varun_agr

1 / 33

Thu Sep 15, 2011 9:32 am RCIngham

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