elektroda.net NewsGroups Forum Index - FPGA
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| Lattice XP2 getting hot and/or reading 0's as JTAG ID | Antti | 6 / 34 | Mon Sep 12, 2011 7:00 pm Antti |
| interfacing Xilinx platform usb jtag with other vendor devic | salimbaba | 3 / 52 | Fri Sep 09, 2011 5:57 pm Uwe Bonnes |
| facing problem in creating ..BMM file with RAMB18X2 | lilaisgr8 | 1 / 39 | Fri Sep 09, 2011 3:12 am Steve |
| POST_CRC in Spartan-6 | Lars | 1 / 39 | Thu Sep 08, 2011 4:17 pm Lars |
| Virtex-6 XC6VHX380T Master SPI Configuration Problems.... | Jesper Kristensen | 2 / 46 | Wed Sep 07, 2011 6:28 am Jesper Kristensen |
What is the advantage of source-syncronization (in SDRAMs)? [  Goto page: 1, 2 ] | valtih1978 | 19 / 94 | Fri Sep 02, 2011 7:58 pm Mawa_fugo |
| 5V FCT TO Cyclone II | majsta | 7 / 60 | Tue Aug 30, 2011 9:33 pm majsta |
| A free lunch | Jan Decaluwe | 5 / 55 | Tue Aug 30, 2011 9:35 am Jan Decaluwe |
| Very cheap Spartan3 board that can be configured by simple U [ Goto page: 1, 2 ] | Giuseppe Marullo | 18 / 96 | Tue Aug 30, 2011 2:31 am Jim Granville |
| Boundary scan | salimbaba | 3 / 38 | Mon Aug 29, 2011 9:38 pm glen herrmannsfeldt |
| Bitstream compression [ Goto page: 1, 2 ] | Rob Gaddi | 15 / 88 | Sat Aug 27, 2011 11:12 pm John Larkin |
| ISE and detecting flowthrus | fpga_me | 2 / 44 | Sat Aug 27, 2011 3:16 am fpga_me |
| extracting D from 1 / D*D | Bert_Paris | 13 / 42 | Fri Aug 26, 2011 7:41 am Bert_Paris |
| Regarding virtex II pro xilinx XC2VP30 FF896 | varun_agr | 1 / 32 | Thu Aug 25, 2011 9:46 am Colin Paul Gloster |
| vhdl:passing generic sized arrays to functions? | Morten Leikvoll | 5 / 40 | Tue Aug 23, 2011 3:11 pm KJ |
| Spartan6 PCB debugging: how badly do you have to screw up fo | karl schrunk | 13 / 66 | Tue Aug 23, 2011 2:48 pm Gabor |
| [actel] resource usage by entity | kclo4 | 2 / 37 | Tue Aug 23, 2011 12:10 pm Steve B |
| Testbench in verilog ps and human interactions don't mix | Giuseppe Marullo | 3 / 38 | Mon Aug 22, 2011 1:49 pm Allan Herriman |
| Altera Flex10K support ? | Nicolas Matringe | 5 / 48 | Mon Aug 22, 2011 8:32 am nmatringe@gmail.com |
| VHDL Basic Question | maxascent | 12 / 36 | Sun Aug 21, 2011 7:40 pm Jonathan Bromley |
| Synthesizable heap-sorter for FPGA - BSD licensed sources | wzab | 4 / 61 | Fri Aug 19, 2011 8:09 pm wzab |
| image storing into BRAM | balajigec | 9 / 49 | Fri Aug 19, 2011 5:52 am balajigec |
| DVI-decoder clock question | Mawa_fugo | 3 / 49 | Wed Aug 17, 2011 10:02 pm Mawa_fugo |
| Help needed to emulate a microcontroller. | foxclab01 | 13 / 39 | Wed Aug 17, 2011 4:58 am Michael Karas |
| Need some engineers | Jody Singleton | 2 / 32 | Tue Aug 16, 2011 4:22 pm Bob Perlman |
| VHDL horror in Xcell 76 | RCIngham | 7 / 51 | Tue Aug 16, 2011 6:12 am E Srikanth |
| Xilinx Coregen, command not found java error | Zach Stechly | 5 / 42 | Fri Aug 12, 2011 3:43 pm Bart Fox |
| to sell: Nallatech H101-PCIXM PCI-X FPGA Accelerator Card (u | mexas | 1 / 39 | Thu Aug 11, 2011 11:11 pm glen herrmannsfeldt |
| Is there a utility to peek and poke PCIe devices | General Schvantzkoph | 5 / 35 | Thu Aug 11, 2011 3:30 pm General Schvantzkoph |
| Newbie PCB | linobi | 8 / 55 | Thu Aug 11, 2011 1:42 pm maxascent |
| Verilog, VHDL, sync and async resets | johnp | 1 / 36 | Thu Aug 11, 2011 4:02 am KJ |
| ISE bug? | Andrew Holme | 8 / 39 | Wed Aug 10, 2011 8:16 pm Bob Perlman |
| QuartusII Ver11.0 programmer problems? | Nial Stewart | 2 / 48 | Wed Aug 10, 2011 11:04 am Nial Stewart |
| FPGA | ECS.MSc.SOC | 2 / 50 | Wed Aug 10, 2011 9:05 am eschabor |
| elf of jpeg code to the microblaze | system85 | 1 / 33 | Mon Aug 08, 2011 4:26 pm Tim Wescott |
| RS232 | ECS.MSc.SOC | 1 / 37 | Sun Aug 07, 2011 2:25 pm Phil Emmup |
| Regarding process time calculation [ Goto page: 1, 2 ] | varun_agr | 16 / 69 | Fri Aug 05, 2011 4:41 pm Tim Wescott |
| die's in different packages | Sharan | 6 / 39 | Fri Aug 05, 2011 6:28 am Ed McGettigan |
| FPGA security, Actel down, now Xilinx too? | Antti | 4 / 83 | Thu Aug 04, 2011 10:01 pm stephen.craven@gmail.com |
| XST 13.1 explodes with generic of enum type with only one me | Jonathan Bromley | 13 / 89 | Wed Aug 03, 2011 8:54 pm Brian Drummond |
| Pipeline stages of the Multiplier core (ISE Coregen) | spman | 1 / 37 | Mon Aug 01, 2011 3:14 pm RCIngham |
| Post-map simulation: timing violation and delays | sdaau | 6 / 80 | Thu Jul 28, 2011 4:36 pm sdaau |
| Question on PCI-express verssus Standard PCI performance | Benjamin Couillard | 6 / 43 | Tue Jul 26, 2011 9:14 pm Morten Leikvoll |
| Issues with Soft-Cores | Slamy | 7 / 55 | Tue Jul 26, 2011 5:58 am Bart Fox |
| synthesizing | ECS.MSc.SOC | 3 / 34 | Mon Jul 25, 2011 6:37 pm Tim Wescott |
| About the setup time of BUFGMUX in Spartan6 | jianhuawow | 1 / 37 | Mon Jul 25, 2011 4:29 pm Dustin |
| FPGA not getting programmed [ Goto page: 1, 2 ] | salimbaba | 16 / 79 | Mon Jul 25, 2011 4:04 pm Dustin Brothers |
| FSL Problem:Data Return and Use | aibk01 | 7 / 45 | Mon Jul 25, 2011 11:33 am Brian Drummond |
| source synchronous DDR bus with non-continuous clock | fpgaace | 8 / 47 | Fri Jul 22, 2011 2:21 pm fpgaace |
| Speed attained by virtex 6 | Fpga.Dev69 | 2 / 43 | Thu Jul 21, 2011 3:56 pm Kolja Sulimma |
