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FPGA Editor - Post Route Simulation after changes in Ncd fil

elektroda.net NewsGroups Forum Index - FPGA - FPGA Editor - Post Route Simulation after changes in Ncd fil

Charles
Guest

Thu Jan 28, 2010 7:55 pm   



Hi All,
I am new to the FPGA design flow. Now I am working on FPGA editor t
make changes in the design. Once I make changes in the ncd file i can hav
either a modified ncd file or a bit file from it (using Bitgen).

My question is that is it possible to do post route simulation from any o
these two files or is there any other way to do it??

Thanks in Advance,

Charles.



---------------------------------------
Posted through http://www.FPGARelated.com

kkoorndyk
Guest

Fri Jan 29, 2010 6:03 pm   



On Jan 28, 1:55 pm, "Charles" <charlesdlam...@gmail.com> wrote:
Quote:
Hi All,
       I am new to the FPGA design flow. Now I am working on FPGA editor to
make changes in the design. Once I make changes in the ncd file i can have
either a modified ncd file or a bit file from it (using Bitgen).

My question is that is it possible to do post route simulation from any of
these two files or is there any other way to do it??

Thanks in Advance,

Charles.

---------------------------------------        
Posted throughhttp://www.FPGARelated.com

Yep. Look at the Command Line Tools User Guide (UG628) for the NetGen
function.
www.xilinx.com/support/documentation/sw.../xilinx11/devref.pdf

Jim Wu
Guest

Sat Feb 27, 2010 7:15 pm   



On Jan 28, 1:55 pm, "Charles" <charlesdlam...@gmail.com> wrote:
Quote:
Hi All,
       I am new to the FPGA design flow. Now I am working on FPGA editor to
make changes in the design. Once I make changes in the ncd file i can have
either a modified ncd file or a bit file from it (using Bitgen).

My question is that is it possible to do post route simulation from any of
these two files or is there any other way to do it??

Thanks in Advance,

Charles.

---------------------------------------        
Posted throughhttp://www.FPGARelated.com

You can run "netgen" command with the modified NCD to generate a
Verilog or VHDL simulation model.

Cheers,
Jim
http://myfpgablog.blogspot.com/

elektroda.net NewsGroups Forum Index - FPGA - FPGA Editor - Post Route Simulation after changes in Ncd fil

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