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FIFO with different widths for input and output

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Guest

Wed Mar 30, 2016 7:57 pm   



I need to read a inputs which is 128 bits wide, but my output is only 16 bits wide. I need to read all the 128 bits. So, having a FIFO would solve my issue.

But now, the thing is that FIFO is generally of a particular width and depth. Having the width same as input will not solve my issue as I will still be reading 128 bits of data.

So, I will have to have width of 16 bits. My question here is that how do I write 128 bits of data into this FIFO, as each memory location would have space to store only 16 bits.

Please help me with this design issue.

Thanks in advance!

rickman
Guest

Thu Mar 31, 2016 12:32 am   



On 3/30/2016 1:57 PM, rajesh.krissh_at_gmail.com wrote:
Quote:
I need to read a inputs which is 128 bits wide, but my output is only 16 bits wide. I need to read all the 128 bits. So, having a FIFO would solve my issue.

But now, the thing is that FIFO is generally of a particular width and depth. Having the width same as input will not solve my issue as I will still be reading 128 bits of data.

So, I will have to have width of 16 bits. My question here is that how do I write 128 bits of data into this FIFO, as each memory location would have space to store only 16 bits.

Please help me with this design issue.


Ignoring the FIFO for a moment, you want to read 128 bits of data in 16
bit chunks. That means you need to read the chunks serially. You can
convert the 128 bit data to serial 16 bit data either before the FIFO (a
16 bit one) or after the FIFO (a 128 bit FIFO). Your choice depending
on the requirements of your design. If you need to stream 128 bit data
into the FIFO on successive clock cycles, you need a 128 bit FIFO. If
the data comes in with sufficient time between samples that you can
serially read the eight 16 bit words into a 16 bit FIFO, then that will
potentially save bits in the FIFO.

Any of this make sense?

In many FPGAs the block RAMs (which are often used for FIFOs) can have
different data widths on the two data ports and automatically do the
muxing to let data be read out in a different width. So the FIFO and
the data mux can all be combined in one element.

--

Rick


Guest

Tue Apr 05, 2016 7:30 am   



Thanks Rick, your suggestion worked well. And I was successfully able to implement it.

I used a FIFO with a width of 128 bits and 16 locations wide. It reads 128 bits of data in 16 bit chunks. Then writes out 16 bits at once with the help of a counter which helps me slide the window to write out from this FIFO. After all the 128 bits are sent then the tail of the FIFO increments and starts sending from the next location.

On Wednesday, March 30, 2016 at 2:32:37 PM UTC-4, rickman wrote:
Quote:
On 3/30/2016 1:57 PM, rajesh.krissh_at_gmail.com wrote:
I need to read a inputs which is 128 bits wide, but my output is only 16 bits wide. I need to read all the 128 bits. So, having a FIFO would solve my issue.

But now, the thing is that FIFO is generally of a particular width and depth. Having the width same as input will not solve my issue as I will still be reading 128 bits of data.

So, I will have to have width of 16 bits. My question here is that how do I write 128 bits of data into this FIFO, as each memory location would have space to store only 16 bits.

Please help me with this design issue.

Ignoring the FIFO for a moment, you want to read 128 bits of data in 16
bit chunks. That means you need to read the chunks serially. You can
convert the 128 bit data to serial 16 bit data either before the FIFO (a
16 bit one) or after the FIFO (a 128 bit FIFO). Your choice depending
on the requirements of your design. If you need to stream 128 bit data
into the FIFO on successive clock cycles, you need a 128 bit FIFO. If
the data comes in with sufficient time between samples that you can
serially read the eight 16 bit words into a 16 bit FIFO, then that will
potentially save bits in the FIFO.

Any of this make sense?

In many FPGAs the block RAMs (which are often used for FIFOs) can have
different data widths on the two data ports and automatically do the
muxing to let data be read out in a different width. So the FIFO and
the data mux can all be combined in one element.

--

Rick


rickman
Guest

Tue Apr 05, 2016 12:38 pm   



On 4/5/2016 2:22 AM, rajesh.krissh_at_gmail.com wrote:
Quote:
Thanks Rick, your suggestion worked well. And I was successfully able to implement it.

I used a FIFO with a width of 128 bits and 16 locations wide. It reads 128 bits of data in 16 bit chunks. Then writes out 16 bits at once with the help of a counter which helps me slide the window to write out from this FIFO. After all the 128 bits are sent then the tail of the FIFO increments and starts sending from the next location.


Great, I'm glad it worked for you! Care to share your code so we can
see exactly what you did?

--

Rick

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