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Jan
Guest

Sun Oct 19, 2008 4:25 pm   



Dear all,

What are the smartest way to make a solo FPGA project capable of field
updates? I'm very new in the FPGA world so I don't much about the
practical use of them. Normally when I uses microcontrollers I make them
updateble via USB, serial or SD cards.

What techniques are possible when I want to avoid having a uP in the
project.

My target is a Xilinx Spartan 3A or 3AN

Regards
Jan

Jim Granville
Guest

Sun Oct 19, 2008 8:46 pm   



Jan wrote:
Quote:
Dear all,

What are the smartest way to make a solo FPGA project capable of field
updates? I'm very new in the FPGA world so I don't much about the
practical use of them. Normally when I uses microcontrollers I make them
updateble via USB, serial or SD cards.

What techniques are possible when I want to avoid having a uP in the
project.

My target is a Xilinx Spartan 3A or 3AN

You may find it very hard to safely avoid a uC entirely.
If your power can fail at any time, you need to avoid a
path-of-no-return. That might mean two copies in the loader
memory, one default boot copy, and a second runable-if-ok
copy.

-jg

Nico Coesel
Guest

Sun Oct 19, 2008 10:07 pm   



Jan <1_at_2.3> wrote:

Quote:
Dear all,

What are the smartest way to make a solo FPGA project capable of field
updates? I'm very new in the FPGA world so I don't much about the
practical use of them. Normally when I uses microcontrollers I make them
updateble via USB, serial or SD cards.

What techniques are possible when I want to avoid having a uP in the
project.

My target is a Xilinx Spartan 3A or 3AN

It is possible to do partial (re-) configuration on Xilinx devices
through JTAG. However I don't know if the FPGA could program itself.
Xilinx has some application notes on this subject. If it turns out to
be possible, you can have a small amount of logic (for example
includign a picoblaze cpu) which can load the rest of the FPGA from
configuration memory and update this memory through a serial port (the
picoblaze package comes with a UART).

--
Programmeren in Almere?
E-mail naar nico_at_nctdevpuntnl (punt=.)

Mike Treseler
Guest

Mon Oct 20, 2008 6:54 pm   



Jan wrote:
Quote:
Dear all,

What are the smartest way to make a solo FPGA project capable of field
updates? I'm very new in the FPGA world so I don't much about the
practical use of them. Normally when I uses microcontrollers I make them
updateble via USB, serial or SD cards.

That's the way to do it.
Save multiple images in flash.
The uP handles networking and
loading images to flash and fpga.

Quote:
What techniques are possible when I want to avoid having a uP in the
project.

You could put the project
on a pci[e] card and have
the host pc do the updates.

-- Mike Treseler

Bryan
Guest

Tue Oct 21, 2008 5:40 am   



I think the MultiBoot feature available in Xilinx FPGAs is especially
useful for field updates. MultiBoot allows you to update the FPGA
while maintaining a failsafe image. Avnet has an example application
note showing how to do this, updating the secondary image in serial
Flash with a new image arriving over ethernet.

"S3A1800DSP Serial Flash Bistream Update over Ethernet" at
https://www.em.avnet.com/common/filetree/0%2C2740%2CRID%3D&CID%3D42106&CCD%3DUSA&SID%3D32214&DID%3DDF2&SRT%3D1&LID%3D32232&PRT%3D0&PVW%3D&PNT%3D&BID%3DDF2&CTP%3DEVK%2C00.html?ACD=3

Bryan

On Oct 19, 9:25am, Jan <1...@2.3> wrote:
Quote:
Dear all,

What are the smartest way to make a solo FPGA project capable of field
updates? I'm very new in the FPGA world so I don't much about the
practical use of them. Normally when I uses microcontrollers I make them
updateble via USB, serial or SD cards.

What techniques are possible when I want to avoid having a uP in the
project.

My target is a Xilinx Spartan 3A or 3AN

Regards
Jan



Guest

Thu Apr 18, 2019 11:45 am   



вторник, 21 октября 2008 г., 6:40:26 UTC+4 пользователь Bryan написал:
Quote:
I think the MultiBoot feature available in Xilinx FPGAs is especially
useful for field updates. MultiBoot allows you to update the FPGA
while maintaining a failsafe image. Avnet has an example application
note showing how to do this, updating the secondary image in serial
Flash with a new image arriving over ethernet.

"S3A1800DSP Serial Flash Bistream Update over Ethernet" at
https://www.em.avnet.com/common/filetree/0%2C2740%2CRID%3D&CID%3D42106&CCD%3DUSA&SID%3D32214&DID%3DDF2&SRT%3D1&LID%3D32232&PRT%3D0&PVW%3D&PNT%3D&BID%3DDF2&CTP%3DEVK%2C00.html?ACD=3

Bryan

On Oct 19, 9:25 am, Jan <1...@2.3> wrote:
Dear all,

What are the smartest way to make a solo FPGA project capable of field
updates? I'm very new in the FPGA world so I don't much about the
practical use of them. Normally when I uses microcontrollers I make them
updateble via USB, serial or SD cards.

What techniques are possible when I want to avoid having a uP in the
project.

My target is a Xilinx Spartan 3A or 3AN

Regards
    Jan


Hi, nobody knows, how to get this reference design. The link doesn't work

Julio Di Egidio
Guest

Fri Apr 19, 2019 7:45 am   



On Thursday, 18 April 2019 12:38:42 UTC+2, polovn...@gmail.com wrote:
Quote:
вторник, 21 октября 2008 г., 6:40:26 UTC+4 пользователь Bryan написал:
I think the MultiBoot feature available in Xilinx FPGAs is especially
useful for field updates. MultiBoot allows you to update the FPGA
while maintaining a failsafe image. Avnet has an example application
note showing how to do this, updating the secondary image in serial
Flash with a new image arriving over ethernet.

"S3A1800DSP Serial Flash Bistream Update over Ethernet" at
https://www.em.avnet.com/common/filetree/0%2C2740%2CRID%3D&CID%3D42106&CCD%3DUSA&SID%3D32214&DID%3DDF2&SRT%3D1&LID%3D32232&PRT%3D0&PVW%3D&PNT%3D&BID%3DDF2&CTP%3DEVK%2C00.html?ACD=3

Bryan

On Oct 19, 9:25 am, Jan <1...@2.3> wrote:
Dear all,

What are the smartest way to make a solo FPGA project capable of field
updates? I'm very new in the FPGA world so I don't much about the
practical use of them. Normally when I uses microcontrollers I make them
updateble via USB, serial or SD cards.

What techniques are possible when I want to avoid having a uP in the
project.

My target is a Xilinx Spartan 3A or 3AN

Hi, nobody knows, how to get this reference design. The link doesn't work


I have simply searched for "S3A1800DSP Serial Flash Bistream Update over
Ethernet", here is the first result I get:

<https://forums.xilinx.com/t5/Embedded-Development-Tools/Bootloader-for-Spartan-6-with-SPI-FLash/td-p/158360>

That said, it is very bad etiquette to resurrect old threads: open a new one,
possibly with links to any old posts or whatever is relevant...

HTH and good luck,

Julio


Guest

Fri Apr 19, 2019 9:45 am   



пятница, 19 апреля 2019 г., 9:02:21 UTC+3 пользователь Julio Di Egidio написал:
Quote:
On Thursday, 18 April 2019 12:38:42 UTC+2, polovn...@gmail.com wrote:
вторник, 21 октября 2008 г., 6:40:26 UTC+4 пользователь Bryan написал:
I think the MultiBoot feature available in Xilinx FPGAs is especially
useful for field updates. MultiBoot allows you to update the FPGA
while maintaining a failsafe image. Avnet has an example application
note showing how to do this, updating the secondary image in serial
Flash with a new image arriving over ethernet.

"S3A1800DSP Serial Flash Bistream Update over Ethernet" at
https://www.em.avnet.com/common/filetree/0%2C2740%2CRID%3D&CID%3D42106&CCD%3DUSA&SID%3D32214&DID%3DDF2&SRT%3D1&LID%3D32232&PRT%3D0&PVW%3D&PNT%3D&BID%3DDF2&CTP%3DEVK%2C00.html?ACD=3

Bryan

On Oct 19, 9:25 am, Jan <1...@2.3> wrote:
Dear all,

What are the smartest way to make a solo FPGA project capable of field
updates? I'm very new in the FPGA world so I don't much about the
practical use of them. Normally when I uses microcontrollers I make them
updateble via USB, serial or SD cards.

What techniques are possible when I want to avoid having a uP in the
project.

My target is a Xilinx Spartan 3A or 3AN

Hi, nobody knows, how to get this reference design. The link doesn't work

I have simply searched for "S3A1800DSP Serial Flash Bistream Update over
Ethernet", here is the first result I get:

https://forums.xilinx.com/t5/Embedded-Development-Tools/Bootloader-for-Spartan-6-with-SPI-FLash/td-p/158360

That said, it is very bad etiquette to resurrect old threads: open a new one,
possibly with links to any old posts or whatever is relevant...

HTH and good luck,

Julio


I also found this topic on the forum. Unfortunately, all links related to this project do not work.


Guest

Mon Jul 08, 2019 5:45 pm   



On Monday, October 20, 2008 at 10:54:20 AM UTC-7, Mike Treseler wrote:
Quote:
Jan wrote:
Dear all,

What are the smartest way to make a solo FPGA project capable of field
updates? I'm very new in the FPGA world so I don't much about the
practical use of them. Normally when I uses microcontrollers I make them
updateble via USB, serial or SD cards.

That's the way to do it.
Save multiple images in flash.
The uP handles networking and
loading images to flash and fpga.

What techniques are possible when I want to avoid having a uP in the
project.

You could put the project
on a pci[e] card and have
the host pc do the updates.

-- Mike Treseler


There are small FPGAs with dual flash that simplify the field upgrade. Look at Lattice MachXO2 or Intel MAX10.

Jon Elson
Guest

Mon Jul 08, 2019 8:45 pm   



On Mon, 08 Jul 2019 09:40:49 -0700, camil.matiska wrote:

Quote:
On Monday, October 20, 2008 at 10:54:20 AM UTC-7, Mike Treseler wrote:
Jan wrote:
Dear all,

What are the smartest way to make a solo FPGA project capable of
field updates?

Xilinx FPGAs can be loaded by serial EPROMS with no external circuits.
Xilinx's own SPROMS are really expensive but I use the SST family, I
think now sold by Atmel. The 1 mbit one I use is $0.89 in small quantity.
One downside is they don't make a DIP version, so I solder them to a
little adapter board, that fits an 8-pin DIP socket.

Of course, you can use an external flash ROM or something like the
Spartan 3 AN with internal flash chip. These can be programmed via a JTAG
tap.

Jon

Per
Guest

Mon Jul 15, 2019 5:45 am   



Hi,
for field update we use the FPGA Programmer from FPGA Cores:
http://www.fpga-cores.com/

We have used this for Spartan 6 and Artix.

elektroda.net NewsGroups Forum Index - FPGA - Field update

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