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Error while opening Layout View using Layout XL in IC614

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elektroda.net NewsGroups Forum Index - Cadence - Error while opening Layout View using Layout XL in IC614

Sam
Guest

Wed Jun 06, 2012 7:36 pm   



Dear all,

I have just migrated to IC614 (OpenAccess verions) from IC514 (CDB version).. I have installed IC614, IUS82, MMSIM101, ASSURA-614 in CentOS 5.8. I am using UMC 180nm technology node. It seems I have properly set the cds.lib, .cdsinit and assura_tech.lib. So, after doing this I just thought to verify that all the licensed features are working fine or not.

So, using Schematic XL I have created a simple inverter and did a transient analysis using ADE (G)XL. It worked fine. Then I tried to open the layout view using Layout XL. But I got the following error message:

"(LX-2063): The technology library 'cdsDefTechLib' contains no constraint groups that have a 'validLayers' or 'validVias' constraint defined. Thus the XL connectivity extractor is disabled. To enable it, add a 'validLayers' constraint to the appropriate constraint group, and ensure that this constraint group is specified by the 'setupConstraintGroup' environment variable."



Please suggest me how to fix this issue.

Regards
Sam

Jean-Marc Bourguet
Guest

Wed Jun 06, 2012 7:37 pm   



Sam <samiran.dam_at_gmail.com> writes:

Quote:
Dear all,

I have just migrated to IC614 (OpenAccess verions) from IC514 (CDB
version). I have installed IC614, IUS82, MMSIM101, ASSURA-614 in CentOS
5.8. I am using UMC 180nm technology node. It seems I have properly set
the cds.lib, .cdsinit and assura_tech.lib. So, after doing this I just
thought to verify that all the licensed features are working fine or not.

So, using Schematic XL I have created a simple inverter and did a
transient analysis using ADE (G)XL. It worked fine. Then I tried to open
the layout view using Layout XL. But I got the following error message:

"(LX-2063): The technology library 'cdsDefTechLib' contains no constraint
groups that have a 'validLayers' or 'validVias' constraint defined. Thus
the XL connectivity extractor is disabled. To enable it, add a
'validLayers' constraint to the appropriate constraint group, and ensure
that this constraint group is specified by the 'setupConstraintGroup'
environment variable."

Using the technology library cdsDefTechLib is very suspicious for a layout
and looks like a set up problem. You probably are trying to create the
layout in a library which doesn't refer to the tech file of UMC 180 nm.

When you create a library, you are proposed 3 or 4 ways to associate it
with a technology library, you should probably make it reference the one in
your PDK.

Yours,

--
Jean-Marc

Sam
Guest

Thu Jun 07, 2012 8:01 am   



On Thursday, 7 June 2012 00:29:30 UTC+5:30, Jean-Marc Bourguet wrote:
Quote:
Sam <samiran.dam_at_gmail.com> writes:

Dear all,

I have just migrated to IC614 (OpenAccess verions) from IC514 (CDB
version). I have installed IC614, IUS82, MMSIM101, ASSURA-614 in CentOS
5.8. I am using UMC 180nm technology node. It seems I have properly set
the cds.lib, .cdsinit and assura_tech.lib. So, after doing this I just
thought to verify that all the licensed features are working fine or not.

So, using Schematic XL I have created a simple inverter and did a
transient analysis using ADE (G)XL. It worked fine. Then I tried to open
the layout view using Layout XL. But I got the following error message:

"(LX-2063): The technology library 'cdsDefTechLib' contains no constraint
groups that have a 'validLayers' or 'validVias' constraint defined. Thus
the XL connectivity extractor is disabled. To enable it, add a
'validLayers' constraint to the appropriate constraint group, and ensure
that this constraint group is specified by the 'setupConstraintGroup'
environment variable."

Using the technology library cdsDefTechLib is very suspicious for a layout
and looks like a set up problem. You probably are trying to create the
layout in a library which doesn't refer to the tech file of UMC 180 nm.

When you create a library, you are proposed 3 or 4 ways to associate it
with a technology library, you should probably make it reference the one in
your PDK.

Yours,

--
Jean-Marc

Thank you, Jean. After seeing your post I realized that after creating the library with the UMC 1800 nm technology files with alias 'UMC180_Analog', I renamed the alias to UMC_18_CMOS. And that was causing the problem. Now everything is working fine.

Thank you once again.


Guest

Tue Jan 31, 2017 1:28 pm   



On Wednesday, June 6, 2012 at 11:06:59 PM UTC+5:30, Sam wrote:
Quote:
Dear all,

I have just migrated to IC614 (OpenAccess verions) from IC514 (CDB version). I have installed IC614, IUS82, MMSIM101, ASSURA-614 in CentOS 5.8. I am using UMC 180nm technology node. It seems I have properly set the cds.lib, .cdsinit and assura_tech.lib. So, after doing this I just thought to verify that all the licensed features are working fine or not.

So, using Schematic XL I have created a simple inverter and did a transient analysis using ADE (G)XL. It worked fine. Then I tried to open the layout view using Layout XL. But I got the following error message:

"(LX-2063): The technology library 'cdsDefTechLib' contains no constraint groups that have a 'validLayers' or 'validVias' constraint defined. Thus the XL connectivity extractor is disabled. To enable it, add a 'validLayers' constraint to the appropriate constraint group, and ensure that this constraint group is specified by the 'setupConstraintGroup' environment variable.."



Please suggest me how to fix this issue.

Regards
Sam


I am facing the same problem, but your solution is not helping.


Guest

Thu Dec 14, 2017 6:03 am   



On Thursday, June 7, 2012 at 1:36:59 AM UTC+8, Sam wrote:
Quote:
Dear all,

I have just migrated to IC614 (OpenAccess verions) from IC514 (CDB version). I have installed IC614, IUS82, MMSIM101, ASSURA-614 in CentOS 5.8. I am using UMC 180nm technology node. It seems I have properly set the cds.lib, .cdsinit and assura_tech.lib. So, after doing this I just thought to verify that all the licensed features are working fine or not.

So, using Schematic XL I have created a simple inverter and did a transient analysis using ADE (G)XL. It worked fine. Then I tried to open the layout view using Layout XL. But I got the following error message:

"(LX-2063): The technology library 'cdsDefTechLib' contains no constraint groups that have a 'validLayers' or 'validVias' constraint defined. Thus the XL connectivity extractor is disabled. To enable it, add a 'validLayers' constraint to the appropriate constraint group, and ensure that this constraint group is specified by the 'setupConstraintGroup' environment variable.."



Please suggest me how to fix this issue.

Regards
Sam


1) Solved it by Tools–>Technology File Manager.

2) Manager –>Attach.. (Select the Design library and attach to proper technology library)

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