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Error in vhdl code

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Guest

Sun Dec 08, 2019 10:22 am   



When i was compiling my vhdl code i got an error.....near "EOF":syntax error...can anyone please tell me why this happens. The error is pointing to the last line of my code. Please help....

Rick C
Guest

Sun Dec 08, 2019 7:21 pm   



On Sunday, December 8, 2019 at 3:22:30 AM UTC-5, sweety...@gmail.com wrote:
> When i was compiling my vhdl code i got an error.....near "EOF":syntax error...can anyone please tell me why this happens. The error is pointing to the last line of my code. Please help....

The tool can't "think", it only knows what it is looking for. Most likely you have a control structure or some formatting feature missing and it is finding the end of the file without the missing syntax.

Go through your code and make sure all your control structures are complete and balanced and make sure all your formatting constructs are complete.

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Rick C.

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Charles Bailey
Guest

Sun Dec 08, 2019 8:21 pm   



On 2019-12-08 02:22, sweetymalutty_at_gmail.com wrote:
Quote:
When i was compiling my vhdl code i got an error.....near "EOF":syntax error...can anyone please tell me why this happens. The error is pointing to the last line of my code. Please help....

You probably have an END statement missing somewhere: end if, end
process, end loop, end case, end architecture, ...

Charles Bailey


Guest

Mon Dec 09, 2019 6:24 am   



On Sunday, December 8, 2019 at 11:51:34 PM UTC+5:30, Charles Bailey wrote:
Quote:
On 2019-12-08 02:22, sweetymalutty_at_gmail.com wrote:
When i was compiling my vhdl code i got an error.....near "EOF":syntax error...can anyone please tell me why this happens. The error is pointing to the last line of my code. Please help....

You probably have an END statement missing somewhere: end if, end
process, end loop, end case, end architecture, ...

Charles Bailey


Thank you so much...it worked....the problem was indeed a missing END statement.

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