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error about synthesis and placement

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Nilesh
Guest

Thu Apr 22, 2004 10:07 am   



hello all
i am having following problem.
i am using PKS for synthesis and place/route my design.
i am using VTVTlib25 0.25 micron design kit.i am reading all my vhdl
files and using do_build_generic for netlist creation.but when i read
technology files using folloing commands,

read_tlf vtvtlib25.tlf
read_lef vtvtlib25.lef

i get following error messages:

==> ERROR: capacitance for routing layer metal1 is not defined
<PLC-503>.
Info: <PLC-501>.
Info: Qplace failed. <PLC-889>.
Overall P&R CPU time = 1.540000 seconds. <PLC-530>.
Command _do_place finished at Wed Apr 7 07:41:05 2004
using 0:0:2 Real time. Current peak memory: 113.834MB


vtvtlib25 has .lef files supplied but did not have .tlf files supplied
with it,so i had to convert them using syn2tlf.
(vtvt have synopsys .lib files supplied with it )
is this error becoz of this conversion???
did i miss something in the conversion ??
as NCSU does mentions about making some changes in the techfile.
please help me through this.

thanks
nilesh

ka
Guest

Fri Apr 23, 2004 5:30 am   



On 22 Apr 2004 02:07:19 -0700, nilesh_study2003_at_yahoo.com (Nilesh)
wrote:

Quote:
hello all
i am having following problem.
i am using PKS for synthesis and place/route my design.
i am using VTVTlib25 0.25 micron design kit.i am reading all my vhdl
files and using do_build_generic for netlist creation.but when i read
technology files using folloing commands,

read_tlf vtvtlib25.tlf
read_lef vtvtlib25.lef

i get following error messages:

==> ERROR: capacitance for routing layer metal1 is not defined
PLC-503>.
Info: <PLC-501>.
Info: Qplace failed. <PLC-889>.
Overall P&R CPU time = 1.540000 seconds. <PLC-530>.
Command _do_place finished at Wed Apr 7 07:41:05 2004
using 0:0:2 Real time. Current peak memory: 113.834MB


vtvtlib25 has .lef files supplied but did not have .tlf files supplied
with it,so i had to convert them using syn2tlf.
(vtvt have synopsys .lib files supplied with it )
is this error becoz of this conversion???
did i miss something in the conversion ??
as NCSU does mentions about making some changes in the techfile.
please help me through this.

thanks
nilesh

I think the actual error is your best guide. It says "capacitance for
routing layer metal1 is not defined". I think you should open the LEF
file and see if it has any capacitances defined. If not, you can add
dummy ones or get some estimate from you tech docs.

elektroda.net NewsGroups Forum Index - Synthesis - error about synthesis and placement

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