Equivalent of SystemVerilog Interface in VHDL?

Mon Aug 23, 2010 9:12 pm   

I was wondering if VHDL-2008 (or newer) includes an equivalent of the
SystemVerilog interface.

Mon Aug 23, 2010 9:12 pm   

On Mon, 23 Aug 2010 11:12:45 -0700 (PDT), Poojan Wagh wrote:


hi Poojan,

No, I don't think it does.

Signals of record type have always been available, and
allow you to do some of the simpler things you can do
with SV interfaces, but you typically need to pass them
through "inout" ports which rather messes things up.

There have been various discussions in the past about
adding directions to individual elements of a record,
but (to the best of my knowledge) that never came to
anything - it doesn't sound very nice anyway.

I don't think it is a good idea to be excessively
envious of SV's interfaces. They look like a really
good idea on the surface, and they have some very
interesting potential applications, but in SV as it
stands today they are so badly broken that it's
pretty much impossible to do anything really
creative with them. (Yes, I can hear the mumblings
in the back row even now... here goes Jonathan
ranting about interfaces for the Nth time....
yawn, yawn...)
--
Jonathan Bromley

Tue Aug 24, 2010 3:57 pm   

On Aug 23, 1:57 pm, Jonathan Bromley <s...@oxfordbromley.plus.com>
wrote:


Apparently, I missed the last N-1 times. What's broken about SV
interfaces? (Feel free to reply directly if this line of questioning
is off-topic for this list.)

Tue Aug 24, 2010 7:27 pm   

On 8/24/2010 5:57 AM, Poojan Wagh wrote:


That was in comp.lang.verilog

-- Mike Treseler

Thu Sep 09, 2010 1:21 am   

On Aug 23, 11:12 am, Poojan Wagh <poojanw...@gmail.com> wrote:

I use records with resolved elements. I have written resolution
functions for integer, real, and time to facilitate this. Not for
RTL. Use it extensively in testbench models. Also cover it in our
VHDL Testbenches and Verification class.

Cheers,
Jim
SynthWorks VHDL Training