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eliminating a DDS

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Tim
Guest

Thu Sep 08, 2016 8:53 pm   



Several FPGAs contain PLLs. The PLLs in the Lattice XO2/XO3 FPGAs have a
zillion dynamically programmable (Wishbone bus) parameters, including
the various dividers and multiplexers, and a spiffy fractional divider
in the feedback path.



On 04/09/2016 19:11, John Larkin wrote:
Quote:


I have a design that will use a DDS synthesizer to generate an
internal trigger rate for a pulse generator. The chip will be a ZYNQ
7020. The required upper frequency limit is maybe 20 MHz. The FPGA
will have the usual, 48 bit or so, phase accumulator and sine lookup
stuff clocked at maybe 100 MHz. The FPGA drives a fast DAC which in
turn drives an LC lowpass filter and a comparator. Standard stuff.

But could such a clock be generated entirely inside the FPGA?


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