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rickman
Guest

Tue Sep 06, 2016 7:30 am   



On 9/5/2016 1:15 PM, Tim Wescott wrote:
Quote:
On Mon, 05 Sep 2016 07:43:31 -0700, BobH wrote:

On 09/04/2016 11:11 AM, John Larkin wrote:


I have a design that will use a DDS synthesizer to generate an internal
trigger rate for a pulse generator. The chip will be a ZYNQ 7020. The
required upper frequency limit is maybe 20 MHz. The FPGA will have the
usual, 48 bit or so, phase accumulator and sine lookup stuff clocked at
maybe 100 MHz. The FPGA drives a fast DAC which in turn drives an LC
lowpass filter and a comparator. Standard stuff.

But could such a clock be generated entirely inside the FPGA?

Just using the MSB of the DDS phase accumulator works, but it will have
one full clock, 10 ns p-p, of jitter. That will be ugly at 20 MHz. I've
got to look into some sort of outboard analog filtering to clean up
that single-bit clock, but I'm not optimistic. DDS is just too weird.

Is the analog signal from your sine generator used elsewhere in the
system? If not, I don't see any advantage to using an external
asynchronous analog comparator on an analog signal. You will pick up at
least one clock cycle of jitter re-syncing the incoming analog signal to
the digital clock. Then you have the jitter from the delays out to the
DAC, the filter delays and the comparator jitter to add in.

If the digital logic for the timing generator is not in the same clock
domain as the system receiving it, you will pick up at least one clock
cycle of jitter in the clock boundary transition.

The only way I can think of to reduce the total jitter is the use as
fast a clock as you can, and keep everything in one clock domain. Then
you only have the clock source jitter that effects the entire system.

Good Luck,
BobH

I can't speak to what John is doing, but if he needs a variable-frequency
pulse train with small jitter for some external purpose, then he needs
some sort of DDS or PLL technique.

Assuming that the FPGA clock is good and steady, one could get a finer
than one-clock resolution by playing tricks like using four or eight
output pins to a current DAC, which then charges a cap, which then feeds
a comparator. Then one wouldn't need to have a whole DDS inside -- but
one would still need some external analog stuff, and one would still need
to depend on the FPGA to have a nice consistent clock edge.


When you say "whole DDS", it's not that much circuitry. Besides, John
said he is using a 48 bit phase accumulator with a table lookup which
will give terrible phase jitter. A table lookup is a very poor choice
given the much better ways of high resolution phase to sine conversions
possible.

I'm not at all familiar with how you would control the current DAC if
you don't use a DDS. Are you suggesting the conversion of phase
directly to analog to create a sawtooth wave with the DAC? I don't
think you want to charge a cap. That would give a curved ramp sawtooth.
Maybe I'm not following at all.

I don't know the Zynq parts, but nearly all other FPGAs have proper
analog PLLs which will greatly reduce jitter. I believe the input
frequency range is somewhat limited, so there may need to be some extra
circuitry with the PLL to get the proper output frequency from the
acceptable input frequencies.

--

Rick C

Rob Gaddi
Guest

Tue Sep 06, 2016 7:50 pm   



rickman wrote:

Quote:
On 9/5/2016 7:47 AM, Mike Perkins wrote:
On 05/09/2016 11:57, rickman wrote:
On 9/4/2016 3:13 PM, Mike Perkins wrote:
On 04/09/2016 19:11, John Larkin wrote:


I have a design that will use a DDS synthesizer to generate an
internal trigger rate for a pulse generator. The chip will be a ZYNQ
7020. The required upper frequency limit is maybe 20 MHz. The FPGA
will have the usual, 48 bit or so, phase accumulator and sine lookup
stuff clocked at maybe 100 MHz. The FPGA drives a fast DAC which in
turn drives an LC lowpass filter and a comparator. Standard stuff.

But could such a clock be generated entirely inside the FPGA?

Just using the MSB of the DDS phase accumulator works, but it will
have one full clock, 10 ns p-p, of jitter. That will be ugly at 20
MHz. I've got to look into some sort of outboard analog filtering to
clean up that single-bit clock, but I'm not optimistic. DDS is just
too weird.

Do you suppose that one of the FPGA PLLs be used to clean up the DDS
clock, scrub the jitter somehow? That could maybe be used over a
modest range, octave maybe, followed by some dividers.

That isn't how FPGA PLLs work. They add jitter rather than removing it!

Aren't you thinking of a digital PLL? The PLL in FPGAs is typically a
standard analog PLL and so *would* remove jitter.


Any other ideas for making a programmable-frequency clock with DDS
sort of resolution, but without all that outboard analog stuff?

I've been playing with sorta DDS in LT Spice, using a quantizer to
approximate the DDS accumulator and DAC, but that's obviously not the
best tool for this.

The jitter of a clock derived from within a FPGA would simply be related
to the clock frequency used.

If you use a 250MHz clock, as per the max frequency of many cheap FPGAs,
then jitter will be 4ns (+ a small bit).

Yes, you are clearly thinking of a digital PLL based on the digital
fabric of the FPGA. I assume John was talking about the dedicated PLLs
found in most FPGAS.

Most of my experience is with Xilinx who I don't believe use analogue PLLs.

Most FPGA PLLs are based on a variable length ring of gates which will
have jitter as gates are switched in and out of the loop.

Can you provide an example of a truly analogue PLL in a mainstream FPGA?

Xilinx uses a DLL, but I thought they also had a PLL capability.
Everyone else uses a PLL. Lattice data sheet for the XP2 says...

sysCLOCK™ PLLs
• Up to four analog PLLs per device
• Clock multiply, divide and phase shifting

Altera Cyclone V says this...

Phase-locked loops
(PLLs)
• Precision clock synthesis, clock delay compensation, and zero delay
buffering (ZDB)
• Integer mode and fractional mode

I don't think you can do zero delay buffering if the adjustment is
digital. Later in the document they say this...

• Jitter attenuation

and

PLL-based clock recovery Superior jitter tolerance

That's pretty compelling.


The Cyclone series I at least know a thing about. There's an internal
octave VCO that you spin up to somewhere in to 600-1300 MHz range, and
then divide down. When I've looked at jitter performance a bit it's
fairly good; below the measurement floor of cheap measurement
equipment. I haven't really gone in with a spectrum analyzer to look
for spurs, but I'd imagine there's not much point to it. That probably
depends heavily on case-by-case power supply bypassing and exact
programmed frequency (as well as whether you're using an integer or
fractional divide) and is hard to talk about in any kind of general
sense.

The Zynq (at least according to the data sheet) does the same thing, VCO
in the 800-2100 MHz range and divide down.

Xilinx says nuttin' about the loop filter bandwidth, but Altera gives
typs for their three switchable filters as 0.3, 1.5, and 4 MHz.

--
Rob Gaddi, Highland Technology -- www.highlandtechnology.com
Email address domain is currently out of order. See above to fix.


Guest

Tue Sep 06, 2016 8:15 pm   



Den tirsdag den 6. september 2016 kl. 19.50.23 UTC+2 skrev Rob Gaddi:
Quote:
rickman wrote:

On 9/5/2016 7:47 AM, Mike Perkins wrote:
On 05/09/2016 11:57, rickman wrote:
On 9/4/2016 3:13 PM, Mike Perkins wrote:
On 04/09/2016 19:11, John Larkin wrote:


I have a design that will use a DDS synthesizer to generate an
internal trigger rate for a pulse generator. The chip will be a ZYNQ
7020. The required upper frequency limit is maybe 20 MHz. The FPGA
will have the usual, 48 bit or so, phase accumulator and sine lookup
stuff clocked at maybe 100 MHz. The FPGA drives a fast DAC which in
turn drives an LC lowpass filter and a comparator. Standard stuff.

But could such a clock be generated entirely inside the FPGA?

Just using the MSB of the DDS phase accumulator works, but it will
have one full clock, 10 ns p-p, of jitter. That will be ugly at 20
MHz. I've got to look into some sort of outboard analog filtering to
clean up that single-bit clock, but I'm not optimistic. DDS is just
too weird.

Do you suppose that one of the FPGA PLLs be used to clean up the DDS
clock, scrub the jitter somehow? That could maybe be used over a
modest range, octave maybe, followed by some dividers.

That isn't how FPGA PLLs work. They add jitter rather than removing it!

Aren't you thinking of a digital PLL? The PLL in FPGAs is typically a
standard analog PLL and so *would* remove jitter.


Any other ideas for making a programmable-frequency clock with DDS
sort of resolution, but without all that outboard analog stuff?

I've been playing with sorta DDS in LT Spice, using a quantizer to
approximate the DDS accumulator and DAC, but that's obviously not the
best tool for this.

The jitter of a clock derived from within a FPGA would simply be related
to the clock frequency used.

If you use a 250MHz clock, as per the max frequency of many cheap FPGAs,
then jitter will be 4ns (+ a small bit).

Yes, you are clearly thinking of a digital PLL based on the digital
fabric of the FPGA. I assume John was talking about the dedicated PLLs
found in most FPGAS.

Most of my experience is with Xilinx who I don't believe use analogue PLLs.

Most FPGA PLLs are based on a variable length ring of gates which will
have jitter as gates are switched in and out of the loop.

Can you provide an example of a truly analogue PLL in a mainstream FPGA?

Xilinx uses a DLL, but I thought they also had a PLL capability.
Everyone else uses a PLL. Lattice data sheet for the XP2 says...

sysCLOCK™ PLLs
• Up to four analog PLLs per device
• Clock multiply, divide and phase shifting

Altera Cyclone V says this...

Phase-locked loops
(PLLs)
• Precision clock synthesis, clock delay compensation, and zero delay
buffering (ZDB)
• Integer mode and fractional mode

I don't think you can do zero delay buffering if the adjustment is
digital. Later in the document they say this...

• Jitter attenuation

and

PLL-based clock recovery Superior jitter tolerance

That's pretty compelling.


The Cyclone series I at least know a thing about. There's an internal
octave VCO that you spin up to somewhere in to 600-1300 MHz range, and
then divide down. When I've looked at jitter performance a bit it's
fairly good; below the measurement floor of cheap measurement
equipment. I haven't really gone in with a spectrum analyzer to look
for spurs, but I'd imagine there's not much point to it. That probably
depends heavily on case-by-case power supply bypassing and exact
programmed frequency (as well as whether you're using an integer or
fractional divide) and is hard to talk about in any kind of general
sense.

The Zynq (at least according to the data sheet) does the same thing, VCO
in the 800-2100 MHz range and divide down.

Xilinx says nuttin' about the loop filter bandwidth, but Altera gives
typs for their three switchable filters as 0.3, 1.5, and 4 MHz.


Zynq datasheet say 1MHz and 4MHz

also says max input clock jitter 20% or 1ns

-Lasse

Kevin Neilson
Guest

Tue Sep 06, 2016 9:11 pm   



On Sunday, September 4, 2016 at 12:11:40 PM UTC-6, John Larkin wrote:
Quote:
I have a design that will use a DDS synthesizer to generate an
internal trigger rate for a pulse generator. The chip will be a ZYNQ
7020. The required upper frequency limit is maybe 20 MHz. The FPGA
will have the usual, 48 bit or so, phase accumulator and sine lookup
stuff clocked at maybe 100 MHz. The FPGA drives a fast DAC which in
turn drives an LC lowpass filter and a comparator. Standard stuff.

But could such a clock be generated entirely inside the FPGA?


You could use a single-bit DAC (like a Sigma-Delta DAC) filtered by a 1-pole RC filter and then run back into an LVDS input. So then you'd just have the RC filter external. But I don't know if the oversampling rate (100MHz/20MHz) is enough precision.

Another option is to use the lower bits of your phase accumulator to add phase to the output using the ODELAY blocks. You can get a precision of 78ps if you use 200MHz as your reference clock. However, I'm not certain how often you can update the ODELAY delay value.

John Larkin
Guest

Wed Sep 07, 2016 2:22 am   



On Sun, 04 Sep 2016 11:11:32 -0700, John Larkin
<jjlarkin_at_highlandtechnology.com> wrote:

Quote:


I have a design that will use a DDS synthesizer to generate an
internal trigger rate for a pulse generator. The chip will be a ZYNQ
7020. The required upper frequency limit is maybe 20 MHz. The FPGA
will have the usual, 48 bit or so, phase accumulator and sine lookup
stuff clocked at maybe 100 MHz. The FPGA drives a fast DAC which in
turn drives an LC lowpass filter and a comparator. Standard stuff.

But could such a clock be generated entirely inside the FPGA?

Just using the MSB of the DDS phase accumulator works, but it will
have one full clock, 10 ns p-p, of jitter. That will be ugly at 20
MHz. I've got to look into some sort of outboard analog filtering to
clean up that single-bit clock, but I'm not optimistic. DDS is just
too weird.

Do you suppose that one of the FPGA PLLs be used to clean up the DDS
clock, scrub the jitter somehow? That could maybe be used over a
modest range, octave maybe, followed by some dividers.

Any other ideas for making a programmable-frequency clock with DDS
sort of resolution, but without all that outboard analog stuff?

I've been playing with sorta DDS in LT Spice, using a quantizer to
approximate the DDS accumulator and DAC, but that's obviously not the
best tool for this.


Well, it's looking like I'll just use an external DDS chip, AD9835
probably, with the usual LC lowpass filter and comparator. I can clock
that from a handy 50 MHz oscillator that we need for the Ethernet phy.

Looks like trying to do this inside the FPGA is too risky, jitter and
such. That close to Nyquist, I will need a good filter.




--

John Larkin Highland Technology, Inc
picosecond timing precision measurement

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

Tim Wescott
Guest

Wed Sep 07, 2016 3:38 am   



On Mon, 05 Sep 2016 22:52:33 -0400, rickman wrote:

Quote:
On 9/5/2016 1:15 PM, Tim Wescott wrote:
On Mon, 05 Sep 2016 07:43:31 -0700, BobH wrote:

On 09/04/2016 11:11 AM, John Larkin wrote:


I have a design that will use a DDS synthesizer to generate an
internal trigger rate for a pulse generator. The chip will be a ZYNQ
7020. The required upper frequency limit is maybe 20 MHz. The FPGA
will have the usual, 48 bit or so, phase accumulator and sine lookup
stuff clocked at maybe 100 MHz. The FPGA drives a fast DAC which in
turn drives an LC lowpass filter and a comparator. Standard stuff.

But could such a clock be generated entirely inside the FPGA?

Just using the MSB of the DDS phase accumulator works, but it will
have one full clock, 10 ns p-p, of jitter. That will be ugly at 20
MHz. I've got to look into some sort of outboard analog filtering to
clean up that single-bit clock, but I'm not optimistic. DDS is just
too weird.

Is the analog signal from your sine generator used elsewhere in the
system? If not, I don't see any advantage to using an external
asynchronous analog comparator on an analog signal. You will pick up
at least one clock cycle of jitter re-syncing the incoming analog
signal to the digital clock. Then you have the jitter from the delays
out to the DAC, the filter delays and the comparator jitter to add in.

If the digital logic for the timing generator is not in the same clock
domain as the system receiving it, you will pick up at least one clock
cycle of jitter in the clock boundary transition.

The only way I can think of to reduce the total jitter is the use as
fast a clock as you can, and keep everything in one clock domain. Then
you only have the clock source jitter that effects the entire system.

Good Luck,
BobH

I can't speak to what John is doing, but if he needs a
variable-frequency pulse train with small jitter for some external
purpose, then he needs some sort of DDS or PLL technique.

Assuming that the FPGA clock is good and steady, one could get a finer
than one-clock resolution by playing tricks like using four or eight
output pins to a current DAC, which then charges a cap, which then
feeds a comparator. Then one wouldn't need to have a whole DDS inside
-- but one would still need some external analog stuff, and one would
still need to depend on the FPGA to have a nice consistent clock edge.

When you say "whole DDS", it's not that much circuitry. Besides, John
said he is using a 48 bit phase accumulator with a table lookup which
will give terrible phase jitter. A table lookup is a very poor choice
given the much better ways of high resolution phase to sine conversions
possible.

I'm not at all familiar with how you would control the current DAC if
you don't use a DDS. Are you suggesting the conversion of phase
directly to analog to create a sawtooth wave with the DAC? I don't
think you want to charge a cap. That would give a curved ramp sawtooth.
Maybe I'm not following at all.

I don't know the Zynq parts, but nearly all other FPGAs have proper
analog PLLs which will greatly reduce jitter. I believe the input
frequency range is somewhat limited, so there may need to be some extra
circuitry with the PLL to get the proper output frequency from the
acceptable input frequencies.


I was thinking along the lines of generating a programmable delay after
the clock tick -- with all due respect for the fact that it won't be
perfect, in a number of ways.

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

I'm looking for work -- see my website!

rickman
Guest

Wed Sep 07, 2016 7:30 am   



On 9/6/2016 4:22 PM, John Larkin wrote:
Quote:
On Sun, 04 Sep 2016 11:11:32 -0700, John Larkin
jjlarkin_at_highlandtechnology.com> wrote:



I have a design that will use a DDS synthesizer to generate an
internal trigger rate for a pulse generator. The chip will be a ZYNQ
7020. The required upper frequency limit is maybe 20 MHz. The FPGA
will have the usual, 48 bit or so, phase accumulator and sine lookup
stuff clocked at maybe 100 MHz. The FPGA drives a fast DAC which in
turn drives an LC lowpass filter and a comparator. Standard stuff.

But could such a clock be generated entirely inside the FPGA?

Just using the MSB of the DDS phase accumulator works, but it will
have one full clock, 10 ns p-p, of jitter. That will be ugly at 20
MHz. I've got to look into some sort of outboard analog filtering to
clean up that single-bit clock, but I'm not optimistic. DDS is just
too weird.

Do you suppose that one of the FPGA PLLs be used to clean up the DDS
clock, scrub the jitter somehow? That could maybe be used over a
modest range, octave maybe, followed by some dividers.

Any other ideas for making a programmable-frequency clock with DDS
sort of resolution, but without all that outboard analog stuff?

I've been playing with sorta DDS in LT Spice, using a quantizer to
approximate the DDS accumulator and DAC, but that's obviously not the
best tool for this.

Well, it's looking like I'll just use an external DDS chip, AD9835
probably, with the usual LC lowpass filter and comparator. I can clock
that from a handy 50 MHz oscillator that we need for the Ethernet phy.

Looks like trying to do this inside the FPGA is too risky, jitter and
such. That close to Nyquist, I will need a good filter.


Then it might be a good idea to use the FPGA to double or quadruple the
50 MHz clock and run the external DDS with that.

--

Rick C

rickman
Guest

Wed Sep 07, 2016 7:30 am   



On 9/6/2016 5:38 PM, Tim Wescott wrote:
Quote:
On Mon, 05 Sep 2016 22:52:33 -0400, rickman wrote:

On 9/5/2016 1:15 PM, Tim Wescott wrote:
On Mon, 05 Sep 2016 07:43:31 -0700, BobH wrote:

On 09/04/2016 11:11 AM, John Larkin wrote:


I have a design that will use a DDS synthesizer to generate an
internal trigger rate for a pulse generator. The chip will be a ZYNQ
7020. The required upper frequency limit is maybe 20 MHz. The FPGA
will have the usual, 48 bit or so, phase accumulator and sine lookup
stuff clocked at maybe 100 MHz. The FPGA drives a fast DAC which in
turn drives an LC lowpass filter and a comparator. Standard stuff.

But could such a clock be generated entirely inside the FPGA?

Just using the MSB of the DDS phase accumulator works, but it will
have one full clock, 10 ns p-p, of jitter. That will be ugly at 20
MHz. I've got to look into some sort of outboard analog filtering to
clean up that single-bit clock, but I'm not optimistic. DDS is just
too weird.

Is the analog signal from your sine generator used elsewhere in the
system? If not, I don't see any advantage to using an external
asynchronous analog comparator on an analog signal. You will pick up
at least one clock cycle of jitter re-syncing the incoming analog
signal to the digital clock. Then you have the jitter from the delays
out to the DAC, the filter delays and the comparator jitter to add in.

If the digital logic for the timing generator is not in the same clock
domain as the system receiving it, you will pick up at least one clock
cycle of jitter in the clock boundary transition.

The only way I can think of to reduce the total jitter is the use as
fast a clock as you can, and keep everything in one clock domain. Then
you only have the clock source jitter that effects the entire system.

Good Luck,
BobH

I can't speak to what John is doing, but if he needs a
variable-frequency pulse train with small jitter for some external
purpose, then he needs some sort of DDS or PLL technique.

Assuming that the FPGA clock is good and steady, one could get a finer
than one-clock resolution by playing tricks like using four or eight
output pins to a current DAC, which then charges a cap, which then
feeds a comparator. Then one wouldn't need to have a whole DDS inside
-- but one would still need some external analog stuff, and one would
still need to depend on the FPGA to have a nice consistent clock edge.

When you say "whole DDS", it's not that much circuitry. Besides, John
said he is using a 48 bit phase accumulator with a table lookup which
will give terrible phase jitter. A table lookup is a very poor choice
given the much better ways of high resolution phase to sine conversions
possible.

I'm not at all familiar with how you would control the current DAC if
you don't use a DDS. Are you suggesting the conversion of phase
directly to analog to create a sawtooth wave with the DAC? I don't
think you want to charge a cap. That would give a curved ramp sawtooth.
Maybe I'm not following at all.

I don't know the Zynq parts, but nearly all other FPGAs have proper
analog PLLs which will greatly reduce jitter. I believe the input
frequency range is somewhat limited, so there may need to be some extra
circuitry with the PLL to get the proper output frequency from the
acceptable input frequencies.

I was thinking along the lines of generating a programmable delay after
the clock tick -- with all due respect for the fact that it won't be
perfect, in a number of ways.


Ok, I got you. That's interesting. It requires the same external
equipment as the traditional sine wave DDS with a DAC, analog filter and
comparator except for the filter with the addition of something to zero
out the integrator. The value fed to the DAC would need to be scaled to
the inverse of the phase step size, a PITA in digital. That likely
would be done in a look up table. This is all feasible, but I don't
know how piratical to get the jitter from 10 ns down to say, 100 ps.

--

Rick C


Guest

Wed Sep 07, 2016 1:10 pm   



On Tuesday, September 6, 2016 at 11:22:12 PM UTC+3, John Larkin wrote:
Quote:

Well, it's looking like I'll just use an external DDS chip, AD9835
probably, with the usual LC lowpass filter and comparator. I can clock
that from a handy 50 MHz oscillator that we need for the Ethernet phy.


AD9835 has single-ended DAC output, right?
I don't see how you achieve jitter in picosecond range when you start with single-ended 20MHz signal followed by filter and comparator. Ground drift alone will put jitter into 10s of ps range, but more likely into over 100 ps.

Another problem is a input clock to AD9835 which is also single-ended and also have relatively low frequency (50 MHz). Again, ground noise would be translated into relatively high jitter.
Or do you say that the all jitter *before* low-pass (or band-pass) filter is of no significance? I am not sure that it is true.

Quote:

Looks like trying to do this inside the FPGA is too risky, jitter and
such. That close to Nyquist, I will need a good filter.




--

John Larkin Highland Technology, Inc
picosecond timing precision measurement

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com



Guest

Wed Sep 07, 2016 9:55 pm   



Den søndag den 4. september 2016 kl. 20.11.40 UTC+2 skrev John Larkin:
Quote:
I have a design that will use a DDS synthesizer to generate an
internal trigger rate for a pulse generator. The chip will be a ZYNQ
7020. The required upper frequency limit is maybe 20 MHz. The FPGA
will have the usual, 48 bit or so, phase accumulator and sine lookup
stuff clocked at maybe 100 MHz. The FPGA drives a fast DAC which in
turn drives an LC lowpass filter and a comparator. Standard stuff.

But could such a clock be generated entirely inside the FPGA?

Just using the MSB of the DDS phase accumulator works, but it will
have one full clock, 10 ns p-p, of jitter. That will be ugly at 20
MHz. I've got to look into some sort of outboard analog filtering to
clean up that single-bit clock, but I'm not optimistic. DDS is just
too weird.

Do you suppose that one of the FPGA PLLs be used to clean up the DDS
clock, scrub the jitter somehow? That could maybe be used over a
modest range, octave maybe, followed by some dividers.

Any other ideas for making a programmable-frequency clock with DDS
sort of resolution, but without all that outboard analog stuff?

I've been playing with sorta DDS in LT Spice, using a quantizer to
approximate the DDS accumulator and DAC, but that's obviously not the
best tool for this.


https://www.dropbox.com/s/h4qdwm9dllgiivh/dds_pll.jpg

ch1, MSB from 100MHz, 32 bit accumulator with some random increment to get ~20MHz
ch2, through a PLL in jitter filtermode

with an increment that results in exactly 25MHz:

https://www.dropbox.com/s/9rizod2e15mxlhs/dds_pll1.jpg


-Lasse

John Larkin
Guest

Wed Sep 07, 2016 10:00 pm   



On Wed, 7 Sep 2016 04:10:32 -0700 (PDT), already5chosen_at_yahoo.com
wrote:

Quote:
On Tuesday, September 6, 2016 at 11:22:12 PM UTC+3, John Larkin wrote:

Well, it's looking like I'll just use an external DDS chip, AD9835
probably, with the usual LC lowpass filter and comparator. I can clock
that from a handy 50 MHz oscillator that we need for the Ethernet phy.


AD9835 has single-ended DAC output, right?
I don't see how you achieve jitter in picosecond range when you start with single-ended 20MHz signal followed by filter and comparator. Ground drift alone will put jitter into 10s of ps range, but more likely into over 100 ps.


Proper PCB layout will prevent ground loop voltages. The DDS output is
a current source, which helps a lot. A passive LC filter can be
terminated at one end, at the comparator.


Quote:

Another problem is a input clock to AD9835 which is also single-ended and also have relatively low frequency (50 MHz). Again, ground noise would be translated into relatively high jitter.


Single-ended logic signals can have fs RMS jitter. Again, ground loops
should be avoided. I can put the 50 MHz XO close to the DDS, and run a
long trace to the Ethernet gadget; it doesn't care much about jitter.


>Or do you say that the all jitter *before* low-pass (or band-pass) filter is of no significance? I am not sure that it is true.

I don't recall saying that. But since I only need an octave clock
range, a bandpass filter will reject both high and low-frequency
jitter that's out of the filter's passband. At an octave bw, it's
about a toss-up between an official bandpass filter and cascaded
lowpass+highpass filters.

A tunable narrowband filter would be cool. It could track the DDS
frequency. There are a few interesting ways to do that. But that would
be work, and a brute-force long elliptical filter would be as good.

All of which is wandering off the FPGA topic.




--

John Larkin Highland Technology, Inc

lunatic fringe electronics


Guest

Thu Sep 08, 2016 12:45 am   



Den onsdag den 7. september 2016 kl. 23.49.29 UTC+2 skrev John Larkin:
Quote:
On Wed, 7 Sep 2016 12:55:12 -0700 (PDT),
lasselangwadtchristensen_at_gmail.com wrote:

Den søndag den 4. september 2016 kl. 20.11.40 UTC+2 skrev John Larkin:
I have a design that will use a DDS synthesizer to generate an
internal trigger rate for a pulse generator. The chip will be a ZYNQ
7020. The required upper frequency limit is maybe 20 MHz. The FPGA
will have the usual, 48 bit or so, phase accumulator and sine lookup
stuff clocked at maybe 100 MHz. The FPGA drives a fast DAC which in
turn drives an LC lowpass filter and a comparator. Standard stuff.

But could such a clock be generated entirely inside the FPGA?

Just using the MSB of the DDS phase accumulator works, but it will
have one full clock, 10 ns p-p, of jitter. That will be ugly at 20
MHz. I've got to look into some sort of outboard analog filtering to
clean up that single-bit clock, but I'm not optimistic. DDS is just
too weird.

Do you suppose that one of the FPGA PLLs be used to clean up the DDS
clock, scrub the jitter somehow? That could maybe be used over a
modest range, octave maybe, followed by some dividers.

Any other ideas for making a programmable-frequency clock with DDS
sort of resolution, but without all that outboard analog stuff?

I've been playing with sorta DDS in LT Spice, using a quantizer to
approximate the DDS accumulator and DAC, but that's obviously not the
best tool for this.


https://www.dropbox.com/s/h4qdwm9dllgiivh/dds_pll.jpg

ch1, MSB from 100MHz, 32 bit accumulator with some random increment to get ~20MHz
ch2, through a PLL in jitter filtermode

Looks like classic DDS squirmies. The PLL is not filtering the jitter
much. With a clock/Fout ratio of 5:1, 0.4 x Nyquist, a DDS and an LC
lowpass filter usually looks pretty good.


maybe it's possible to have the filter and then run it back in to the FPGA and through fpga PLL? though lowest BW for the PLL is 1MHz

I tried upping the clock to 400MHz and it got quite a lot better, but I've only got a TDS210 scope here so it's hard to tell how much better


Quote:

A PLL, considered as a tracking bandpass filter, could potentially be
a good DDS cleanup.


put the DDS inside the loop ?

Quote:


with an increment that results in exactly 25MHz:

https://www.dropbox.com/s/9rizod2e15mxlhs/dds_pll1.jpg


That's the moral equivalent of dividing 100 MHz by 4!


I know, it was a sanity check ;)



-Lasse

John Larkin
Guest

Thu Sep 08, 2016 3:49 am   



On Wed, 7 Sep 2016 12:55:12 -0700 (PDT),
lasselangwadtchristensen_at_gmail.com wrote:

Quote:
Den sndag den 4. september 2016 kl. 20.11.40 UTC+2 skrev John Larkin:
I have a design that will use a DDS synthesizer to generate an
internal trigger rate for a pulse generator. The chip will be a ZYNQ
7020. The required upper frequency limit is maybe 20 MHz. The FPGA
will have the usual, 48 bit or so, phase accumulator and sine lookup
stuff clocked at maybe 100 MHz. The FPGA drives a fast DAC which in
turn drives an LC lowpass filter and a comparator. Standard stuff.

But could such a clock be generated entirely inside the FPGA?

Just using the MSB of the DDS phase accumulator works, but it will
have one full clock, 10 ns p-p, of jitter. That will be ugly at 20
MHz. I've got to look into some sort of outboard analog filtering to
clean up that single-bit clock, but I'm not optimistic. DDS is just
too weird.

Do you suppose that one of the FPGA PLLs be used to clean up the DDS
clock, scrub the jitter somehow? That could maybe be used over a
modest range, octave maybe, followed by some dividers.

Any other ideas for making a programmable-frequency clock with DDS
sort of resolution, but without all that outboard analog stuff?

I've been playing with sorta DDS in LT Spice, using a quantizer to
approximate the DDS accumulator and DAC, but that's obviously not the
best tool for this.


https://www.dropbox.com/s/h4qdwm9dllgiivh/dds_pll.jpg

ch1, MSB from 100MHz, 32 bit accumulator with some random increment to get ~20MHz
ch2, through a PLL in jitter filtermode


Looks like classic DDS squirmies. The PLL is not filtering the jitter
much. With a clock/Fout ratio of 5:1, 0.4 x Nyquist, a DDS and an LC
lowpass filter usually looks pretty good.

A PLL, considered as a tracking bandpass filter, could potentially be
a good DDS cleanup.


Quote:

with an increment that results in exactly 25MHz:

https://www.dropbox.com/s/9rizod2e15mxlhs/dds_pll1.jpg


That's the moral equivalent of dividing 100 MHz by 4!

Thanks, interesting stuff.




--

John Larkin Highland Technology, Inc
picosecond timing precision measurement

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

John Larkin
Guest

Thu Sep 08, 2016 5:38 am   



On Wed, 7 Sep 2016 15:45:26 -0700 (PDT),
lasselangwadtchristensen_at_gmail.com wrote:

Quote:
Den onsdag den 7. september 2016 kl. 23.49.29 UTC+2 skrev John Larkin:
On Wed, 7 Sep 2016 12:55:12 -0700 (PDT),
lasselangwadtchristensen_at_gmail.com wrote:

Den sndag den 4. september 2016 kl. 20.11.40 UTC+2 skrev John Larkin:
I have a design that will use a DDS synthesizer to generate an
internal trigger rate for a pulse generator. The chip will be a ZYNQ
7020. The required upper frequency limit is maybe 20 MHz. The FPGA
will have the usual, 48 bit or so, phase accumulator and sine lookup
stuff clocked at maybe 100 MHz. The FPGA drives a fast DAC which in
turn drives an LC lowpass filter and a comparator. Standard stuff.

But could such a clock be generated entirely inside the FPGA?

Just using the MSB of the DDS phase accumulator works, but it will
have one full clock, 10 ns p-p, of jitter. That will be ugly at 20
MHz. I've got to look into some sort of outboard analog filtering to
clean up that single-bit clock, but I'm not optimistic. DDS is just
too weird.

Do you suppose that one of the FPGA PLLs be used to clean up the DDS
clock, scrub the jitter somehow? That could maybe be used over a
modest range, octave maybe, followed by some dividers.

Any other ideas for making a programmable-frequency clock with DDS
sort of resolution, but without all that outboard analog stuff?

I've been playing with sorta DDS in LT Spice, using a quantizer to
approximate the DDS accumulator and DAC, but that's obviously not the
best tool for this.


https://www.dropbox.com/s/h4qdwm9dllgiivh/dds_pll.jpg

ch1, MSB from 100MHz, 32 bit accumulator with some random increment to get ~20MHz
ch2, through a PLL in jitter filtermode

Looks like classic DDS squirmies. The PLL is not filtering the jitter
much. With a clock/Fout ratio of 5:1, 0.4 x Nyquist, a DDS and an LC
lowpass filter usually looks pretty good.

maybe it's possible to have the filter and then run it back in to the FPGA and through fpga PLL? though lowest BW for the PLL is 1MHz


Yeah, there is jitter cleanup, but it only lasts about 100 ns. The PLL
is pretty fast.


--

John Larkin Highland Technology, Inc
picosecond timing precision measurement

jlarkin att highlandtechnology dott com
http://www.highlandtechnology.com

rickman
Guest

Thu Sep 08, 2016 7:30 am   



On 9/7/2016 6:45 PM, lasselangwadtchristensen_at_gmail.com wrote:
Quote:
Den onsdag den 7. september 2016 kl. 23.49.29 UTC+2 skrev John Larkin:
On Wed, 7 Sep 2016 12:55:12 -0700 (PDT),
lasselangwadtchristensen_at_gmail.com wrote:

Den søndag den 4. september 2016 kl. 20.11.40 UTC+2 skrev John Larkin:
I have a design that will use a DDS synthesizer to generate an
internal trigger rate for a pulse generator. The chip will be a ZYNQ
7020. The required upper frequency limit is maybe 20 MHz. The FPGA
will have the usual, 48 bit or so, phase accumulator and sine lookup
stuff clocked at maybe 100 MHz. The FPGA drives a fast DAC which in
turn drives an LC lowpass filter and a comparator. Standard stuff.

But could such a clock be generated entirely inside the FPGA?

Just using the MSB of the DDS phase accumulator works, but it will
have one full clock, 10 ns p-p, of jitter. That will be ugly at 20
MHz. I've got to look into some sort of outboard analog filtering to
clean up that single-bit clock, but I'm not optimistic. DDS is just
too weird.

Do you suppose that one of the FPGA PLLs be used to clean up the DDS
clock, scrub the jitter somehow? That could maybe be used over a
modest range, octave maybe, followed by some dividers.

Any other ideas for making a programmable-frequency clock with DDS
sort of resolution, but without all that outboard analog stuff?

I've been playing with sorta DDS in LT Spice, using a quantizer to
approximate the DDS accumulator and DAC, but that's obviously not the
best tool for this.


https://www.dropbox.com/s/h4qdwm9dllgiivh/dds_pll.jpg

ch1, MSB from 100MHz, 32 bit accumulator with some random increment to get ~20MHz
ch2, through a PLL in jitter filtermode

Looks like classic DDS squirmies. The PLL is not filtering the jitter
much. With a clock/Fout ratio of 5:1, 0.4 x Nyquist, a DDS and an LC
lowpass filter usually looks pretty good.

maybe it's possible to have the filter and then run it back in to the FPGA and through fpga PLL? though lowest BW for the PLL is 1MHz

I tried upping the clock to 400MHz and it got quite a lot better, but I've only got a TDS210 scope here so it's hard to tell how much better



A PLL, considered as a tracking bandpass filter, could potentially be
a good DDS cleanup.

put the DDS inside the loop ?


I don't see how that can matter. The DDS will in general create jitter
of one clock period in regardless of what that clock is. If the PLL
doesn't filter jitter in the reference, is it likely to filter jitter in
the feed back clock?

--

Rick C

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