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EDK : FSL macros defined by Xilinx are wrong

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AL
Guest

Sun Feb 20, 2005 7:49 am   



Hi Jason, But isn't that for simulation only? I want something to display after I download the program to the FPGA and ran it. Thanks, Ann

server
Guest

Fri Apr 21, 2006 10:49 pm   



message unavailable

Austin Lesea
Guest

Fri Apr 21, 2006 10:49 pm   



All,

Here is the answer:

"Hi,

Yes this is a bug. This issue is being fixed for the next EDK release
(8.2i). Also, your patches seem correct."

Austin

Austin Lesea wrote:

Quote:
Sylvain,

I got it.

I will find out what happened, and report back.

Thanks,

Austin

Sylvain Munaut wrote:

Can anyone @Xilinx can confirm they read this and will take
care of it ?


Sylvain Munaut wrote:

Hi everyone,

I hope someone @Xilinx will read this.

In the new EDK 8.1 the FSL access macros have changed
name. And they also introduced _interruptible versions.
Theses are defined in
${EDK_HOME}/sw/lib/bsp/standalone_v1_00_a/src/microblaze/mb_interface.h

The definitions for getfsl_interruptible and
cgetfsl_interruptible are correct. But the ones for
putfsl_interruptible and cputfsl_interruptible are
incorrect. For example putfsl_interruptible is :

#define putfsl_interruptible(val, id) \
asm volatile ("\n1:\n\tnput\t%0,rfsl" #id "\n\t" \
"addic\tr18,r0,0\n\t" \
"bnei\tr18,1b\n" \
: "=d" (val) :: "r18")

and it should be :

#define putfsl_interruptible(val, id) \
asm volatile ("\n1:\n\tnput\t%0,rfsl" #id "\n\t" \
"addic\tr18,r0,0\n\t" \
"bnei\tr18,1b\n" \
:: "d" (val) : "r18")

Obviously val is a input in the case of a 'put' and not
an output.


Another related question : In my code, when a replace all
non _interruptible versions by their _interruptible counter
parts, it doesn't behave as excpected anymore ...
Does theses version require some hw support ?



Sylvain



PS: I know I should submit a webcase but when I try to login
I just get "Server Error" ... and so I obviously can't even
submit a webcase about my problem of being unable to log in
into the webcase ...



Guest

Fri Apr 21, 2006 10:49 pm   



"black" <mini_monkey_at_163.net> writes:

Quote:
hi Jonathan Bromley:
The reason for using FPGA's dedicated clock distribution resources is
that there is no clock skew in these resources,is that right?

There is skew even in dedicated clock lines. Because clock nets are
dedicated for just for clock signals skew is much smaller and can
(more easily) be accounted for in place and route. Most FPGA tools
warn about gated clocks because then your skew is no longer well known
parameter of global clock net but depends heavily on your design.


--
Keijo Länsikunnas

Luiz Carlos
Guest

Fri Apr 21, 2006 10:49 pm   



Quote:
but these are SIMD, not-GP, registers.

As far as I know, its the same core of the Toshiba TX7901 micro
processor, and it has 32 (of course, itīs a MIPS) 128 bit registers,
although the two integer units are 64 bits wide. Only the SIMD
intructions use all 128 bits (32bitx4, 16 bitX8 or 8bitx16 data
types). There are no special porpouse SIMD registers.

Luiz Carlos.

Jonathan Bromley
Guest

Fri Apr 21, 2006 10:49 pm   



"black" <mini_monkey_at_163.net> wrote in message
news:bdrkmo$vq2ne$1_at_ID-199450.news.dfncis.de...

Quote:
The reason for using FPGA's dedicated
clock distribution resources is
that there is no clock skew in these resources,is that right?

There is always *some* skew, but whatever it is, the FPGA
manufacturer guarantees that if you use the dedicated clock
network then you will never suffer from the skew-related
race condition that we discussed.

When designing ASICs and custom ICs, you achieve the same
result by using specialised clock tree insertion software.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: jonathan.bromley_at_doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

Christian Haase
Guest

Fri Apr 21, 2006 10:49 pm   



Hi tk,

thanks for your reply.

I had to get more familiar with the the buff-stuff. An ibufg is just a
dedicated input buffer
for connecting to the clock buffer BUFG or CLKDLL.The clock problem was
solved
with the insertion of a BUFG.

Actually, my dwarfish design is routed on a Virtex-II device using the
Xilinx xapp290
example bus-macro. Maybe the format of that macro (created with a former
FPGA-Editor
version) differs slightly from the format of the self-made macros?

Christian

rickman
Guest

Fri Apr 21, 2006 10:49 pm   



Luiz Carlos wrote:
Quote:

Again, I don't think you are reading what I am posting. In the XC3S400
there are almost 7200 FFs and LUTs. So there are nearly 3600 LUTs
capable of being RAMs and SRs. How many do you really need??? That is
56,000 bits of distributed RAM, almost a quarter as much as the block
rams! Don't you need some LUTs to use as logic???

The wider address rams will require external muxing/control to
implement with only 4 LUTs/CLB usable as ram rather than 8.

That is my poit of view. I donīt care (not much) of having just half
of the LUTs confurable as memory (Iīve read what you wrote, Rick), but
I didnīt like loosing those dual ported bigger blocks (you didnīt read
carefully what I wrote). To have the same function I'll need a lot of
additional logic and/or a clock two times faster. So, my DSP designs
need a lot of more CLBs in Spartan3 than in Virtex2, and I'm not Ray.

Luiz Carlos Oenning Martins
KHOMP Solutions

You can feel how you wish about your designs, but even the loss of the
64 bit dual ports and the 128 bit single port rams is not signficant.
To make a 64 bit dual port RAM requires 8 LUTs for ram (same as in VII)
and one LUT for the read mux and possibly two more LUTs for the WEs.
But if this is part of a larger ram block you are making half of the WEs
would have been required anyway. So it is not a "large" amount of
logic, just a bit more.

If you are making really large blocks where the longer runs on the
address and data can slow it down significantly, then you likely are
better off with the block rams.

Considering the much lower price of the XC3S parts, all this sounds to
me like a benefit, not a liability. Think of it as paying for the LUTs
that have RAM and getting the other LUTs for free :)

--

Rick "rickman" Collins

rick.collins_at_XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

Colm Clancy
Guest

Fri Apr 21, 2006 10:49 pm   



Thomas,

Ngdbuild is warning that what it thinks is a clock (but is actually a reset) is
not connected to clock pins of various components. When I have seen this
warning it was usually as a result of having some non clock nets driven by a
clock buffer, i.e. a bufg.

Colm.

Thomas wrote:

Quote:
I get the following warning:

WARNING:NgdBuild:477 - clock net 'resetlogic_local_reset' has non-clock
connections. These problematic connections include: pin clr on block
resetlogic_resettimer_3 with type FDCE, pin pre on block
resetlogic_resettimer_0 with type FDPE, pin pre on block
resetlogic_logicreset with type FDPE, pin pre on block
resetlogic_resettimer_1 with type FDPE, pin pre on block
resetlogic_cpureset
with type FDPE, pin pre on block resetlogic_resettimer0_1 with type
FDPE, pin
pre on block resetlogic_resettimer0_0 with type FDPE, pin pre on block
resetlogic_resettimer_2 with type FDPE, pin pre on block
resetlogic_resettimer_4 with type FDPE

... that signal is a reset signal that stays low for a few clocks then goes
high. What does this message mean?
the xilinx doc, is (once again | as usual | as expected ) useless at
describing what it is.


Peter Alfke
Guest

Fri Apr 21, 2006 10:49 pm   



rickman wrote:
Quote:


Except that I often am contacted by Altera directly rather than here in
public. I can understand why they would do that.

I cannot understand that at all. If the question is ventilated in
public, it should be answered in public. Unless the answer is very embarrassing...

Peter Alfke, Xilinx

Peter Alfke
Guest

Fri Apr 21, 2006 10:49 pm   



Perhaps I did not explain well enough:
Use the asynchronous reset the way you want to.
Then generate a synchronous signal that lasts a little longer than the
asynchronous reset, and use this synchronous reset signal to either
drive Clock Enable inactive, or to force D Low. This overrides the
trailing end of the asynchronous Resst, and lets the flip-flop "wake up"
in a synchronous fashion, which is easy to simulate...
Peter Alfke
===================
Nial Stewart wrote:
Quote:

Peter Alfke <peter_at_xilinx.com> wrote in message
news:3F00A341.650BCCA4_at_xilinx.com...
My approach would be to generate a synchronous CE (clock disable) signal
and distribute it. Now I have a synchronous signal distribution problem
that I can analyze the conventional way. If the prop delay is less than
a clock period, there is no problem. Otherwise I can resort to
pipelining...
That means, you are in charge and not at the mercy of some loosely
specified asynchronous delay

Peter, do you recommend using these synchronised resets with the asynch
reset
input of your flip-flops, or do they then become part of the
synchronous inputs?

Nial.
------------------------------------------------
Nial Stewart Developments Ltd
FPGA and High Speed Digital Design
www.nialstewartdevelopments.co.uk


Peter Alfke
Guest

Fri Apr 21, 2006 10:49 pm   



Sorry, this was meant to be a personal reply, and it says that I have
Spartan3-50s here in my drawer. They do exist !
(BTW, don't use your German dictionary, it starts with some colloquialisms...)
Peter
===============
Peter Alfke wrote:
Quote:

Willste nen S3-50 haben? Die liegen hier in meiner Schublade...
Darmstadt ist ja nicht so sehr "out in the wild"
Gruss
Peter
======================
Uwe Bonnes wrote:

DK <dknews_at_ueidaq.com> wrote:
: Hi, All

: for the new multichannel filter design I have a choice -
: Altera Cyclone EP1C12 ($60) or Xilinx Spartan-3 XC3S1000(???)

: Xilinx part has a embedded MAC units.

: I've used in a past Altera chips and they have a good tech support and free
: tools.

: Does any one has experience with Xilinx support? And is it possible to
: obtain a free tools from Xilinx or they charge for the software?

: Any other hidden issues?

Don't expect the Spartan III out in the wild any soon...

Bye
--
Uwe Bonnes bon_at_elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------


Antti Lukats
Guest

Fri Apr 21, 2006 10:49 pm   



"tk" <tokwok_at_hotmail.com> wrote in message news:<bde307$j68$1_at_www.csis.hku.hk>...
Quote:
Hi all,

I have problem in configuring the xc2vp7 on the ML300 board. The
problem is described in the previous thread "ERROR:iMPACT:583".

I doubt that I have omitted some settings on the ML300 board during
programming (or have done sth wrong in iMPACT). There is a button
called "FPGA PROG" on the ML300 board. I've searched through the
documentation but I couldn't find out what's it for.

Does anyone have the experience on using ML300 that can share with me ?

Thanks very much.

tk

there is not much I can share (yet) but:

the impact/xps download to ML300 freezes some times, problem has been
fixed by restarting rebooting, sometimes pressing the "fpga prog" button.

the fpga prog button I guess simply forces the fpga to not-init state
waiting for config, as sysace is not reset, it stays in non-configured
state until you configure with impact.

there are no settings on ML300 that could prevent the jtag re-config
it should always work (but does not)

in my case I had started v2pdk shells, debug server debugger, killed
them and then tryied impact, and was freeting, not sure why.

antti

Mike Randelzhofer
Guest

Fri Apr 21, 2006 10:49 pm   



"Peter Alfke" <peter_at_xilinx.com> wrote in message
news:3F01ACDB.D6932AAE_at_xilinx.com...
Quote:
Willste nen S3-50 haben? Die liegen hier in meiner Schublade...
Darmstadt ist ja nicht so sehr "out in the wild"
Gruss
Peter
======================
Uwe Bonnes wrote:

DK <dknews_at_ueidaq.com> wrote:
: Hi, All

: for the new multichannel filter design I have a choice -
: Altera Cyclone EP1C12 ($60) or Xilinx Spartan-3 XC3S1000(???)

: Xilinx part has a embedded MAC units.

: I've used in a past Altera chips and they have a good tech support and
free
: tools.

: Does any one has experience with Xilinx support? And is it possible to
: obtain a free tools from Xilinx or they charge for the software?

: Any other hidden issues?

Don't expect the Spartan III out in the wild any soon...

Bye
--
Uwe Bonnes bon_at_elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Hab auch ein paar S3-50 in der Schublade...
Weiss aber immer noch nicht ob die Blockrams und DLL's haben oder nicht ?

Gruss MIKE

for our english readers:
I also have some spartan3-50 devices, but don't know if they have blockrams
and dll's ?

regards MIKE

Antonio Pasini
Guest

Fri Apr 21, 2006 10:49 pm   



"Jun" <free_y2003_at_yahoo.com> ha scritto nel messaggio
news:vc32gvkddvihro1o7ukstsqu6ue6l9bhdv_at_4ax.com...
Quote:
I am now designing a FPGA based video processing board for my own use.
The board has standard NTSC/PAL, HD and DVI input., a VirtexII FPGA,
64 bit DDR-SDAM interface, DVI/RGB/YPbPr output, I2C and UART
communication port. Recently, I heard some interests from others

I'd purchase one myself, should that contains also:

- a strip for piggy back modules, with at least 8 bit + clock + 3 ctrl
lines, to test different decoders, or different receivers.
- an NTSC/PAL encoder
- a Firewire port ? or maybe pushing up a bit the "piggy back" interface...
- the HD input can scale down to SDI ?

Keep us informed, seems really interesting.

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