EDK : FSL macros defined by Xilinx are wrong

Wed Feb 17, 2010 3:08 am   

On Feb 16, 7:07 pm, Weng Tianxiang <wtx...@gmail.com> wrote:


The reason twofold. One is that the pin was not called ALE on the
latch, it was called C or G or LE or something similar. ALE is from
the Intel CPUs that require the latch to hold the address bits. The
other reason is that you are looking at the wrong part. The 373 part
is the latch and the 374 part is the register. I am pretty sure the
only difference is the function of the clock input.

The latch is used with these processors for the exact reason you are
looking at latches. It allows the output of the latch to output a
stable value from the input before the clock edge rather than after.
This was used to speed memory accesses.

Rick

Wed Feb 17, 2010 3:32 am   

rickman <gnuarm_at_gmail.com> wrote:
(snip)


I still remember latches from when I first started learning about
TTL from Popular Electronics. It was usual to connect a 7490 counter,
a 7475 latch and 7447 BCD to 7 segment decoder together. You run
the counter, the display counts (maybe too fast to see), and then
latches at the appropriate time. Sort of like a lap timer in
a race, which counts up, the latch holds the value while the
counter continues on. After a short time the count continues
on for the next lap. (I think they do this on olympics races.)

-- glen

Thu Feb 18, 2010 3:12 am   

On Feb 16, 5:38 pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote:

glen,
I found a very good example on how to use a latch.

See Xilinx's patent: 5933369 "RAM with synchronous write port using
dynamic latches".

It describes the method Xilinx uses for its distributed RAM.

Weng

Thu Feb 18, 2010 7:28 pm   

Weng,

Maybe we are using this patent, maybe not.

Just because it is a Xilinx patent does not automatically mean we
actually do this now, or ever.

Austin

Fri Feb 19, 2010 3:33 am   

On Feb 18, 9:28 am, austin <aus...@xilinx.com> wrote:

Hi Austin,
Whether or not Xilinx uses the technique doesn't matter to me, I am
not working for Altera or any other FPGA companies, what matters to me
is the technique itself behind the patent.

Those are techniques you cannot learn from any textbooks.

Thank Xilinx, I learn a lot by reading Xilinx's patents.

Weng

Wed Mar 03, 2010 7:24 pm   

Have had good luck with both. Active-HDL supports command line equivalen
of ModelSim. One issue, the "default" format for the Active-HDL waveform
is large and slow (??). I think it was an extra license (cost) for th
fast format. I don't recall which version of Active-HDL we had but i
might be worth checking before a purchase.

Another small note, Mentor had FAE locally (CO) that was useful. Didn'
have as good access to Aldec FAE. But maybe I never needed to ask, so i
was needed, can't remember?

We ran all simulations from scripts (command line) and both worked fro
that perspective.

.chris



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Thu Mar 04, 2010 5:07 pm   

That might be true, does anyone know what the level of SystemVerilo
support is in Active-HDL. Back in 2005 was using Modelsim-PE wit
SystemVerilog fine, support all features I used then, class, interface
etc. BOMK it has been expanded since then.

You can get 30 day eval of both (pretty sure). Might be worth trying ou
unless there is a show stopper like SystemVerilog or multi-languag
support, Active-HDL supports Verilog/VHDL without an extra license (
think).

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Thu Mar 04, 2010 6:07 pm   

I have been using both Modelsim PE and Active HDL since last six years
over the years , I have seen noticeable speed advantage of 2-3 times i
Active HDL-PE compared to Modelsim-PE. I also use lot of scripts t
simulate my designs and link files to AHDL without making local copies i
AHDL project.Well there is definite cost advantage with active HDL-PE.

-Nick



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Thu Mar 04, 2010 7:05 pm   

On Mar 4, 8:07 am, "cfelton" <cfelton_at_n_o_s_p_a_m.ieee.org> wrote:

BOMK?

Thu Mar 04, 2010 10:10 pm   

On Mar 4, 10:05 am, d_s_klein <d_s_kl...@yahoo.com> wrote:

"best of my knowledge."

-a

Thu Mar 11, 2010 10:19 pm   

The extra processing steps for the TFT do cost more. However, the die
size reduction swamps that out to create a low cost FPGA. The ASIC
gets rid of that extra cost and benefits from the yield improvement
for an even lower cost solution.

All I can tell you is come get a quote and we can save you money.
Xilinx and Altera love all the skepticism here and want you to
conitnue paying too much for your solutions.

Regards,

Jeff

Thu Mar 11, 2010 10:31 pm   

Hello,

Tier Logic wrote:

I assume that you have been too long in "stealth mode".

Now I tell you this :
"show me your public price list, your products,
demo boards, detailed datasheet and distributors.
Then maybe I'll choose you for a project".

I'll take the example of a competitor.
SiliconBlue has maybe "slow" chips
(according to only one test I did) but they got
it almost right for the rest, at least for me :
- decent development tool (not bloated)
that installs easily on Linux AND Windows !
- datasheet and other informations, enough to understand
how it is ticking inside so it can be used
- at least one distributor that talks to anyone
(even though the distributor is not large,
at least it does its job and doesn't scare potential customers)
- unit price that is decent is small quantities.
- ultra-low power is a plus but not critical for me.

And still it's not functional enough for me.
Antti has developped for it and I'm curious.
Now before you can save me money, try to beat SBt,
and then... beat the others
The Actel ProAsic3 family is working very fine
for me and wonder how it can be displaced.

good luck,



--
http://ygdes.com / http://yasep.org

Thu Mar 11, 2010 11:31 pm   

-jg wrote:

and the distributors sing to the same tune.

I met Future and Actel France
today at the annual parisian Actel seminar,
I was not interested by their new offering,
I'm waiting for an eventual next generation with
a better SRAM/logic ratio.


HE has the boards and can tell more acurate
stories than mine.

I "only" installed their SW, and tried to
compile a simple adder design, probably
http://yasep.org/VHDL/asu_rop2/testdiff.vhd (test nr 1)
http://yasep.org/VHDL/asu_rop2/ASU_ROP2_16.vhd
and got such a low MHz rating that I thought
that I hit the wrong button or something like that.
I tweaked many stuff and could not influence
the result much, tried different architectures...
and I gave up.
It just means that it did not meet my expectations.
I know that SBt's chips are created for ultraultralow power
and low speed. I'm not expecting Virtex performance
but i'm demanding anyway ;-)

If you want acurate figures, I prefer that you
try yourself, because i'm not sure why it is slow.
i've read "80MHz performance" or something like that
in the datasheets at the time
but like other FPGA claims, i'm not able to reach them.
I've seen people able to do about 300MHz designs
with ProASIC, I can only do 100MHz and Actel's
soft ARM maxes at around 60MHz... for a chip that
is meant to be "able of 350MHz".

so test yourself :-)



--
http://ygdes.com / http://yasep.org

Thu Mar 11, 2010 11:37 pm   

On 11 Mrz., 21:19, Tier Logic <jeff.ka...@gmail.com> wrote:

Isnt the biggest area in FPGAs covered by routing (lines & switches)
which are still present in Tier Logic?

Anyway it looks interesting to me and i have registered to evaluate
further...

But one thing i am concerned with is design security of the
programmable devices.

Thu Mar 11, 2010 11:40 pm   

On Mar 11, 12:19 pm, Tier Logic <jeff.ka...@gmail.com> wrote:

Jeff, you should be ashamed of that cheap shot, especially when Austin
earlier today invited the audience to check out your alleged lower
prices.
I can understand when a newcomer is aggressive in his claims, and
nebulous in his explanations. But do not get sarcastic and nasty.
You still have a lot to prove before you can climb on a high horse.
Peter Alfke