EDK : FSL macros defined by Xilinx are wrong

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On Nov 26, 9:22 am, whygee <y...@yg.yg> wrote:
So... what's left ?
It's not clear exactly what you are asking ?
I'm asking for more ideas or methods

Epson, EM Microelectronic et al, have 32Khz osc
modules, that include the crystal.
all I have seen up to now at my usual sources

Maxim have one that is TCXO as well, and
if precision matters, then you will need txco.
The precision that I need is crystal-like,

NXP PCF2129 is another candidate, but less stocked.
Never heard about this part...

MicroCrystal.com also have a range.
hmmm yet another new name for me

Some tcxo's are fixes in time, not frequency, so
watch the details
I'll watch them but what do you mean exactly ?

-jg
yg

If this is for motion control,
it's likely the 40ns jitter and 5ppm of
my earlier example is fine...
By "motion control" I mean something similar to

.. but in case it is not, if you are going to x4 the 25MHz anyway in a
PLL, then this can apply :
I've thought about this, since I target operation 100MHz in the digital domain.

1-((1*(3051/100e6)+3*(3052/100e6))/4)*32768
ans = 2.56e-6
That's a complex computation, the PLL's dividers

ie from 100MHz, you get 2.56ppm, and 10ns jitter,
and any binary time under 32768/4, has no jitter
at all.

-jg
jg != malcolm ?

I think you've covered all the bases given your apparently conflicting
requirements. Often engineering is a matter of determining an optimal
combination of all requirements, but sometimes it is a matter of
trading off one against the other so that neither is optimal, but both
are adequate.
Yeah, I remember reading a Usenet poster's signature along these lines

So if you *must* use 25 MHz, then you need a 25 MHz
oscillator, not 24.576.
right.

That means you have to provide another
clock. If using a 32.576 kHz oscillator is too power consuming,
at least if I do it myself, because I'm not sure to do it right.

how do you expect to get this second clock? I don't see how a clock chip
would be any better than a 32.576 kHz oscillator. The clock chip
still uses a crystal.
I first thought about using an integrated external clock/calendar

Rick
yg

-jg wrote:

The precision that I need is crystal-like,
but I fear that if I do my own circuit,
I can't tune it to reach it.
Compensation capacitors, track parasites etc.
can spoil the circuit unnecessarily.
So a canned osc sounds best.

Some tcxo's are fixes in time, not frequency, so
watch the details ;)

I'll watch them but what do you mean exactly ?

On Nov 26, 12:17 pm, whygee <y...@yg.yg> wrote:
So I think the jitter is not critical, but overall stability is desirable.
Commercial temperature range is OK.
But a cheap, long-term stable, pre-tuned oscillator for clocks/calendars
would have been good : it could keep track of time/date AND provide real-time signals
If those last few ppm matter, you will pay for them...
sure... i'll go for the price first

1-((1*(3051/100e6)+3*(3052/100e6))/4)*32768
ans = 2.56e-6
That's a complex computation, the PLL's dividers
are too small for division by 3051...
Not complex : You divide 100MHz by 3051 one out of 4 times, and 3 out
of 4 times, you divide by 3052. So that's just 12FF for the 3051/3052
counter, and 2FF for the 'which of 4? counter'
It seems that it's too demanding, the FF are not the whole story.

-jg
jg != malcolm ?
My son grabs his gmail, and I don't always notice....
erf

-jg
yg

malcolm wrote:
If this is for motion control,
it's likely the 40ns jitter and 5ppm of
my earlier example is fine...

By "motion control" I mean something similar to
Microchip's AN964 : "Software PID Control of an Inverted Pendulum Using the PIC16F684 "http://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeI...

So I think the jitter is not critical, but overall stability is desirable..
Commercial temperature range is OK.
But a cheap, long-term stable, pre-tuned oscillator for clocks/calendars
would have been good : it could keep track of time/date AND provide real-time signals

1-((1*(3051/100e6)+3*(3052/100e6))/4)*32768
ans = 2.56e-6

That's a complex computation, the PLL's dividers
are too small for division by 3051...

-jg

jg != malcolm ?

On Dec 4, 6:39 am, "Nial Stewart"

nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote:
FPGA design using a PCB layout tool is a recipe for disaster.

Indeed, I think they're wasting their time down this path.

What is good is the ability to pin/netlist swap when routing and pass
that back to the FPGA constraints. They should concentrate on this and making it
as flexible as possible but forget the FPGA development side of things.

Is the tool FPGA pin type aware?  I have found some layout people
don't like to swap pins on FPGAs because it can be very complex due to
the many constraints on pin capability.  If the tool is aware of these
limitations, it could help with intelligent swapping.

Andy Peters <goo...@latke.net> writes:
On Dec 7, 6:26 am, Martin Thompson <martin.j.thomp...@trw.com> wrote:
laserbeak43 <laserbea...@gmail.com> writes:
Hello,
    I've just been shownSignaltap, A feature inQuartusWebpack
Edition. Does the Webpack Edition of ISE have this feature? WOW this
alone can convince me to use Altera products.

Chipscope is theXilinxequivalent - it's not in webpack (personally, I
think that's a mistake onXilinx'spart)

But comparing it toSignaltapmay (IMHO) leave you underwhelmed... it's
very disjointed and unintegrated in comparison.  I'm still using FPGA
editor to change which signals to monitor, then having to update the
viewer by hand! V. tedious.

Really? Whatversionof ChipScope are you using?

10.1.3



Use the ChipScope Core Inserter.

Indeed, I could (and have in the past), but

a) I'm using the EDK variety of core inserter, as it manages the JTAG
linkages with the microblaze debug module for me

b) I then have to run MAP, PAR, bitgen again.

All of the signals and elements of
the design are shown in it, and you simply choose the signals to
monitor. After you close the Inserter, go back to ISE, and re-fit.

Re-fit - 10s of minutes.

From the ChipScope viewer, you can reconfigure the FPGA, then do an
"Import" which lets you bring in the names of all of the signals you
selected from the ChipScope Core Inserter project file.

No need to go into the FPGA editor at all!

FPGAeditor, regenerate bitstream, 10s of seconds...  Then click "write
CDC" button, import the result into the analyser.  Still tedious :)

As I recall my experience withSignalTap(which was a while ago
admittedly) I could select a signal from a dropdown list *in the
Analyser* and it would do the tedious hacking that I currently do in
FPGAed, regen the bitstream and upload it for me.

Under some circumstances, it would redo a fit at that point, which was
irritating, but at least I was able to do it all from the analyzer GUI,
which was then always in sync with the FPGA.

[Followups set to comp.arch.fpga, as it's not very Veriloggy]

Cheers,
Martin

Crosspost & Followup-To: comp.arch.fpga
--
martin.j.thomp...@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technologyhttp://www.conekt.net/electronics.html

Andy Peters <goo...@latke.net> writes:
On Dec 7, 6:26 am, Martin Thompson <martin.j.thomp...@trw.com> wrote:
laserbeak43 <laserbea...@gmail.com> writes:
Hello,
    I've just been shown Signaltap, A feature in Quartus Webpack
Edition. Does the Webpack Edition of ISE have this feature? WOW this
alone can convince me to use Altera products.

Chipscope is the Xilinx equivalent - it's not in webpack (personally, I
think that's a mistake on Xilinx's part)

But comparing it to Signaltap may (IMHO) leave you underwhelmed... it's
very disjointed and unintegrated in comparison.  I'm still using FPGA
editor to change which signals to monitor, then having to update the
viewer by hand! V. tedious.

Really? What version of ChipScope are you using?

10.1.3



Use the ChipScope Core Inserter.

Indeed, I could (and have in the past), but

a) I'm using the EDK variety of core inserter, as it manages the JTAG
linkages with the microblaze debug module for me

b) I then have to run MAP, PAR, bitgen again.

All of the signals and elements of
the design are shown in it, and you simply choose the signals to
monitor. After you close the Inserter, go back to ISE, and re-fit.

Re-fit - 10s of minutes.

From the ChipScope viewer, you can reconfigure the FPGA, then do an
"Import" which lets you bring in the names of all of the signals you
selected from the ChipScope Core Inserter project file.

No need to go into the FPGA editor at all!

FPGAeditor, regenerate bitstream, 10s of seconds...  Then click "write
CDC" button, import the result into the analyser.  Still tedious :)

As I recall my experience with SignalTap (which was a while ago
admittedly) I could select a signal from a dropdown list *in the
Analyser* and it would do the tedious hacking that I currently do in
FPGAed, regen the bitstream and upload it for me.

Under some circumstances, it would redo a fit at that point, which was
irritating, but at least I was able to do it all from the analyzer GUI,
which was then always in sync with the FPGA.

[Followups set to comp.arch.fpga, as it's not very Veriloggy]

Cheers,
Martin

Crosspost & Followup-To: comp.arch.fpga
--
martin.j.thomp...@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technologyhttp://www.conekt.net/electronics.html

I can't even get this simple code to work in the inserter

module two_input_xor (
        input wire in1,
        input wire in2,
        output wire out
        );
        assign out = in1 ^ in2;
endmodule

On Dec 9, 6:48 am, Martin Thompson <martin.j.thomp...@trw.com> wrote:



Andy Peters <goo...@latke.net> writes:
On Dec 7, 6:26 am, Martin Thompson <martin.j.thomp...@trw.com> wrote:
laserbeak43 <laserbea...@gmail.com> writes:
Hello,
    I've just been shown Signaltap, A feature in Quartus Webpack
Edition. Does the Webpack Edition of ISE have this feature? WOW this
alone can convince me to use Altera products.

Chipscope is the Xilinx equivalent - it's not in webpack (personally, I
think that's a mistake on Xilinx's part)

But comparing it to Signaltap may (IMHO) leave you underwhelmed... it's
very disjointed and unintegrated in comparison.  I'm still using FPGA
editor to change which signals to monitor, then having to update the
viewer by hand! V. tedious.

Really? What version of ChipScope are you using?

10.1.3

Use the ChipScope Core Inserter.

Indeed, I could (and have in the past), but

a) I'm using the EDK variety of core inserter, as it manages the JTAG
linkages with the microblaze debug module for me

b) I then have to run MAP, PAR, bitgen again.

All of the signals and elements of
the design are shown in it, and you simply choose the signals to
monitor. After you close the Inserter, go back to ISE, and re-fit.

Re-fit - 10s of minutes.

From the ChipScope viewer, you can reconfigure the FPGA, then do an
"Import" which lets you bring in the names of all of the signals you
selected from the ChipScope Core Inserter project file.

No need to go into the FPGA editor at all!

FPGAeditor, regenerate bitstream, 10s of seconds...  Then click "write
CDC" button, import the result into the analyser.  Still tedious :)

As I recall my experience with SignalTap (which was a while ago
admittedly) I could select a signal from a dropdown list *in the
Analyser* and it would do the tedious hacking that I currently do in
FPGAed, regen the bitstream and upload it for me.

Under some circumstances, it would redo a fit at that point, which was
irritating, but at least I was able to do it all from the analyzer GUI,
which was then always in sync with the FPGA.

[Followups set to comp.arch.fpga, as it's not very Veriloggy]

Cheers,
Martin

Crosspost & Followup-To: comp.arch.fpga
--
martin.j.thomp...@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technologyhttp://www.conekt.net/electronics.html- Hide quoted text -

- Show quoted text -

Hi,
I finally understand the reason when a flip-flops can be replaced by a
latch.
I saw the circuits before, but not realized what the basic reason was.
With the above paper, I now know that the technology is not a new, it
originated in 1980s.

On Feb 12, 9:05 am, Weng Tianxiang <wtx...@gmail.com> wrote:

Hi,
I finally understand the reason when a flip-flops can be replaced by a
latch.
I saw the circuits before, but not realized what the basic reason was.
With the above paper, I now know that the technology is not a new, it
originated in 1980s.

Even earlier than that.

 Just look at the relative sales volumes of the venerable 74373 vs
74374.
 In all those cases, the latch is used to buy some extra setup time.

 Anywhere you find an ALE pin, you find this principle, and that goes
back a LONG way.

-jg

On Feb 16, 12:36?pm, -jg <jim.granvi...@gmail.com> wrote:

Even earlier than that.

?Just look at the relative sales volumes of the venerable 74373 vs
| 74374. In all those cases, the latch is used to buy some extra
| setup time.

?Anywhere you find an ALE pin, you find this principle, and that
| goes back a LONG way.

I checked SN74LV374 TI's manual and couldn't find what you
said: ALE pin.