EDK : FSL macros defined by Xilinx are wrong

Sorry if this was asked once before ....

ATT is shutting down USENET for its residential DSL subscribers.

Is there a web portal to comp.arch.fpga anywhere?

I'd have to have to pay for third-party usenet if it can be avoided.

thanks
Bob Smith



news-supp...@sbcglobal.net wrote:
Please note that on July 15, 2009, AT&T will no longer be offering
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I find there are any number of aspects of the VHDL language that I
just do not remember and I am not going to make up flash cards to help
me remember. So I drag a half dozen VHDL books around with me when I
am working on VHDL (or much less frequently, Verilog; one of the books
covers both).

I am getting tired of heaving the books up into the truck every time I
go to the lake and am starting to wonder if I should invest in some
good e-books on HDL.

What do the rest of you prefer? Do you have both? Do you still need
to rely on your books or do you pretty well have the language down
pat?

On Jul 28, 6:55 pm, John Larkin
jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
On Tue, 28 Jul 2009 15:12:35 -0700, "Joel Koltner"



zapwireDASHgro...@yahoo.com> wrote:
http://i.cmpnet.com/eetimes/news/09/07/1565chart_pg18.gif

Interesting, indeed.

Cypress had viable products but I'm convinced that management was the problem.
(I also remember they wanted a rather large premium for their CPLDs that were
sometimes only marginally better than the competition's.)

I don't know what Vantis's problem was, but at least after Lattive bought them
they kept a few of the parts around.

Intel doesn't have its heart in much of anything but their desktop CPUs --
they consistently bring out interesting products and then discontinue them
just when they're starting to gain traction.

You're pretty much a pure Xilinx man these days, aren't you, John?

Yes, although I occasionally use a 22V10 for glue logic and such.
We've used MMI, Gould/AMI, Actel, TI, and Lattice in the past.

We've been meaning to start using some CoolRunner type CPLDs for
various things, but no compelling application has come up.

Where the hell are the Spartan 6's? Nobody will tell me when we can
get some. Sales reps fall off the face of the Earth when you ask that
question. The best I can get is "available for purchase in September"
and nobody knows what that means.

So what else is new about Xilinx??? Same old, same old...

I don't get all worked up about the latest and greatest tech in FPGA
chips. I am much more concerned with availability and price than I am
getting the smallest geometry or the most developed technology. So
much of that stuff is actually in the noise when building a product.
I care how well my vehicle moves, the MPG and how often it goes in the
shop. Why should I care how many cylinders, how many valves or even
if it is electric?

With FPGAs, I care about if I can actually get them, will my design
fit (along with any future expansion allowance) and how much it costs,
optionally with what packaging if that matters in a given design. The
rest is in the noise including, for the top three, the tool set.

"Philip Pemberton" <usenet09_at_philpem.me.uk> wrote in message
news:00b7c995$0$4795$c3e8da3_at_news.astraweb.com...

Signetics were definitely before MMI.

Yes. I remember marking up fuse maps by hand,
then sending them away to Signetics and waiting
for a couple of days to get the parts back.

After a few weeks we got an upgrade to our
programmer that allowed us to program without
trashing too many parts (as long as we blasted them
with freeze spray during programming).

Pete

ehl...@isy.liu.se wrote:
1. Compile all source code files with +acc so that it is possible to
   add signals to the wave window.
2. Run simulation for 1 hour or until an error occurs.
3. If no error occured, save a checkpoint with a unique serial number,
   go back to step 2
4. At this point you can load up the latest checkpoint, add all
   relevant signals to your wave window (or signal log if you like the
   log-command) and rerun the simulation

The advantage of this approach is that you don't have to spend any
computation
time to log signal changes while retaining the ability to have full
visibility
when you are actually close to an error.

Look for the checkpoint command in the Modelsim documentation for more
info.

A simple do-script to run the simulation while a signal ("simulate" in my
case) is true, creating numbered checkpoints every 5 ms:

    # Quit simulation after assertion failure (avoids endless loop of just
    # writing checkpoints).
    #
    onbreak {quit -f}

    # Run the simulation as long as the simulate signal is set
    #
    set n 0
    while {[examine /tc/tb/simulate]} {
      incr n
      run 5 ms
      checkpoint chkpnt_$n
    }

If an error occurs, load the checkpoint that was created before the error,
enable tracing and continue simulation.

But please do test if a generated checkpoint can be loaded and the
simulation can continue from that checkpoint.

My experience is that either loading or continuing simulation does not work
on a unsupported platform like Fedora Core 6 or 8. On a platform that is
supported (like Redhat entreprise) it does work.

All I'm saying is: test if it works on your system before simulating for
days.

--
Paul Uiterlindenwww.aimvalley.nl
e-mail addres: remove the not.- Hide quoted text -

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So far I have received no response to the email which I sent to
announceme...@Altera.com on October 12th, 2009. I am not pleased.

Colin Paul Gloster

Did you give them your email address? Is this spam or you just don't
like the fact that it is much harder for them to meet the regulations
of dozens of countries than it is to only make the offer in the single
country where most of their business comes from?

On 2009-10-15, rickman <gnu...@gmail.com> wrote:

Did you give them your email address?  Is this spam or you just don't
like the fact that it is much harder for them to meet the regulations
of dozens of countries than it is to only make the offer in the single
country where most of their business comes from?

On a related note: is it possible Xilinx is giving out mail addresses to
other companies?

I use separate disposable mail addresses for each web registration, and I
just got spam from a Mentor Graphics user group, sent to the mail address
that I only used at xilinx.com. Guess I'll have to disable that account on
my mail server.

cu
Michael

Hi,

This question isn't directly related to FPGAs, I felt people may be able
to help.

I am trying to generate PWM pulses of width 'W' in sync to a square wave
signal X . Please refer Fig1.http://brsharath.googlepages.com/
24102009.jpg

I tried to delay the signal X using logic gates and xored the delayed
signal with the original signal, to get pulses whose ON time equals the
sum of the propagation delay of the logic gates.

See Fig 2 http://brsharath.googlepages.com/24102009001.jpg

Though I am able to see the pulses on the oscilloscope, I see ringing at
the falling edge of the pulse.

What is the cause of ringing ?, and

Are there any alternative ways of generating PWM pulses.

I tried to delay the signal X using logic gates and xored the delayed
signal with the original signal, to get pulses whose ON time equals
the sum of the propagation delay of the logic gates.

See Fig 2http://brsharath.googlepages.com/24102009001.jpg

Though I am able to see the pulses on the oscilloscope, I see ringing
at the falling edge of the pulse.

What is the cause of ringing ?, and

On Oct 24, 6:19 am, Sharath Raju <brshar...@gmail.com> wrote:

I tried to delay the signal X using logic gates and xored the delayed
signal with the original signal, to get pulses whose ON time equals
the sum of the propagation delay of the logic gates.

There are parts called delay lines that generate controlled delays of
specified amounts.
I wasn't aware of them. Thanks

logic is a design that can be depending upon unspecified behavior.
Does the part you're using specify both a minimum and a maximum prop
delay?  If not, how do you guarantee a minimum pulse width coming
out?  Presumably you have a requirement for that.

See Fig 2http://brsharath.googlepages.com/24102009001.jpg

Though I am able to see the pulses on the oscilloscope, I see ringing
at the falling edge of the pulse.

What is the cause of ringing ?, and

The output impedance of the driver does not match the impedance of the
circuit board and the receiver.  Add either a ~33 ohm resistor in
series with the output pin or tack on a ~50 ohm resistor to ground
across the output.  Either method will get rid of most of your
ringing.
shall try that and see.

Kevin Jennings
thanks

Are there any alternative ways of generating PWM pulses.