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Jim Granville
Guest

Fri Apr 21, 2006 10:49 pm   



Chris_S wrote:
<snip>
Quote:
The Altera people told me that a new CPLD family is coming out soon. It
will be lower power. Sounds like Altera has gotten very sick of hearing
their parts are current hogs.

Can they elaborate on the 'out soon', in this industry, that can reach
to the end of 2004 Smile

Quote:
Xilinx says that they also have a new CR (2.5V) part coming out, but it will
probably replace the XC2 line, not XPLA3. They say XPLA3 is not going to be
obsolete.

This sounds a little mangled, and someone from Xilinx may enlighten us.
It may be that the 'new' CoolRunner is the XC2 family ?

The XC2 is so new, only the XC2C256 gives web supply hits.

Once released, a device will only go obsolete if volumes get too small,
or the FAB line closes. The latter happened to Lattice and Xilinx, but
only affected design lines they purchased.

-jg

Jim Granville
Guest

Fri Apr 21, 2006 10:49 pm   



rickman wrote:
Quote:

Chris_S wrote:
snip> > The Altera people told me that a new CPLD family is coming out

soon. It
Quote:
will be lower power. Sounds like Altera has gotten very sick of hearing
their parts are current hogs.

Did they give you a schedule by any chance? If they don't have a
schedule then you shouldn't expect it within the year. Oh, yeah, don't
expect it to be 5 volt tolerant. If you only need LVTTL, then you
should be ok, but all newer devices are 5 volt phobic.

Not entirely - the new Lattice devices offer 5V tolerance, but they
also spec 'no more than 32 IO' at a time.
Strange spec, how does one IO 'know' the state of another ?!

On some devices the IO tolerance is spec'd also CORE relative, so
you can get caught if your IO power is present, and the core
voltage is not!

Lattice appear to be using on-chip regulators, so the multi-rail dance
is showing signs of simplifying. The regulator is a bit 'ordinary', so
the
Icc goes up on those variants.
There are uC being released with regulated core voltages (eg
AT89C51ED2)
so that is a sensible solution, esp for the smaller CPLD's

-jg

Daniel Lang
Guest

Fri Apr 21, 2006 10:49 pm   



Hello,

NRZ (Non-Return to Zero) has only two signalling levels. NRZI is a
non-return to zero code where a 0 is represented by a transition in
the signal and a 1 is represented by no transition. Note that the
NRZ codes are not inherently self clocking, either an external clock
or some method of limiting the number of bit intervals with no
transitions is needed. See
http://wombat.doc.ic.ac.uk/foldoc/foldoc.cgi?Non+Return+To+Zero

Return to Zero (RZ)
http://wombat.doc.ic.ac.uk/foldoc/foldoc.cgi?Return+To+Zero
often used bipolar + and - voltages for 1 and 0, returning to zero volts
between bits (3 level signalling).

Daniel Lang

Quote:
guest> wrote in message news:ee7e625.2_at_WebX.sUN8CHnE...
Dear Falk & Peter,
Thanks for replying, As Iam basic to this information, Please correct me
if iam wromg
NRZ coding say it doesn't return to 0v. For transmitting '1' +V is used
and for transmitting '0' -V volt is used.
we have signalling standards like LVTTL, TTL, CMOS they represent '1' as +V
and '0' as 0V .
What do i say the chip, which provides the NRZ interface,
1) Its signalling varies from +v to -v doesn't return to 0V
2) Or it has used NRZ coding over Some (say CMOS) signalling standard
then one is represented by + Vdd and zero is represented by 0V, am I

wright..?
Quote:
3) what is NRZ, is it not an line coding, i.e how to represent the 1 and 0
across the physical link ?
Thanks in Advance


Jay
Guest

Fri Apr 21, 2006 10:49 pm   



You mean the warning is a suggestion for the simulation process.
and nothing wrong with the model ISE generated.

"Sandeep Kulkarni" <sandeep_at_insight.memec.co.in> 写入消息新闻
:be15fd$27q4$1_at_ID-199516.news.dfncis.de...
Quote:
Hello,
The "glbl.v" module connects the global signals to the design, which makes
it necessary to compile this module with the other design files and to
load
it along with the "toplevel.v" file or the "testbench.v" file for
simulation.

You need to compile it in the simulator, with the timing netlist.

Sandeep
"Jay" <yuhaiwen_at_hotmail.com> wrote in message
news:be0h4j$117mq8$1_at_ID-195883.news.dfncis.de...
in ISE project navigator, when I run the 'generate post-PAR simulation
model' process, I get a warning below:

WARNING:NetListWriters:108 - In order to compile this verilog file
successfully, please add $XILINX/verilog/src/glbl.v to your compile
command.

I'm using a GUI software, how can I change its default command line
under
the button?





Jay
Guest

Fri Apr 21, 2006 10:49 pm   



Really good idea.
but it can't cover all the situation, when I want to divide the clock by 4,
8...
maybe use glbl.GSR is a common solution.
"jetmarc" <jetmarc_at_hotmail.com>
??????:af3f5bb5.0307021455.6db3d07e_at_posting.google.com...
Quote:
I know the reason. without a reset signal to give it a initial value of
'0'
or '1', the clkout will keep the value 'x' during simulation.

In VHDL you can write:

process (clkin)
begin
if rising_edge(clkin) then
if clkout='0' then
clkout <= '1';
else
clkout <= '0';
end if;
end if;
end process;

That works both in the chip, and in the simulator. The trick is that
the ELSE statement covers both '1' and 'x'.

Marc


Bill
Guest

Fri Apr 21, 2006 10:49 pm   



Lasse Langwadt Christensen <langwadt_at_ieee.org> wrote in message news:<3F0371D7.30906_at_ieee.org>...
Quote:
Bill wrote:
"Leon Heller" <leon_heller_at_hotmail.com> wrote in message news:<bdv712$oki$1_at_hercules.btinternet.com>...

eholbrook_at_austin.rr.com> wrote in message
news:874r24dalp.fsf_at_vole.holby-net...

I'm looking for a DIMM format FPGA board like Pilchard or the AcB from
(now defunct?) Nuron. I've done several web searches, but found
nothing that both fits the bill, and is from a company that is
apparently alive. I've found a couple of things that are close to what
i want (from mite.cz, and sunrise-systems.de), but they don't return
emails, so i figure they're dead, too.

Has anyone heard of something like this, or do i need to design/build
it myself?

I was thinking of developing one. How about us collaborating?

Leon



From what I hear, SRC Computers holds patents in this area and is not
licensing to anyone right now.

www.srccomp.com

What!

maybe I read it too fast maybe I just can't read patents or maybe
I just don't understand, but don't they basically claim that they
have patented programble logic memory mapped on a microprocessor?

I would have guessed that that is widely used and has been for some
time :)

-Lasse


I think your reading it right, I would have thought it was widely used as well.

Yu Haiwen
Guest

Fri Apr 21, 2006 10:49 pm   



"John_H" <johnhandwork_at_mail.com> wrote in message news:<1GEKa.20$%E1.13818_at_news-west.eli.net>...
Quote:
"Jay" <yuhaiwen_at_hotmail.com> wrote in message
news:bde3rr$rs8gp$1_at_ID-195883.news.dfncis.de...
snip
How can I simulate this modules? in testbench I tried to initiate the
clkout, but failed.
/snip

If you're doing RTL simulation from your original code, you need to
initialize all your variables for simulation such as

initial
mydesign.clkout <= 1'b0;

Alternatively, post place and route simulation can give you proper
initializations as long as you bring out the global set/reset signal (.GSR)
when generating the verilog file from the Xilinx tool. Then, the "initial"
block doesn't initialize the individual RTL registers but is used to drive
the .GSR for a short time at the start of the simulation, initializing all
the register primitives to the power-on values. I don't recall if memories
still need manual initialization or not (since they aren't cleared by a
reset but are loaded with the programming file).

The advantage to post place and route simulation is that some of your
registers may power up logic high (when an FDS or FDSE primitive is used to
implement the synthesized logic) and an incorrect initial state can alter
your device's performance.

I change the code to
reg clkout;
wire GSR;

always@(posedge clkin)
begin
if(GSR == 1)
clkout <= 0;
else
clkout <= ~clkout;
end

thus in testbench I can give the clkout a initial value.
the simulation can work now.

but I still a little confuse about what you say:
the .GSR can "initializing all the register primitives to the power-on values."
how can it achieve this?
Do I miss someting important?

Antti Lukats
Guest

Fri Apr 21, 2006 10:49 pm   



Thanks Peter,

and sorry xilinx, affiliates, etc, my first comments on ml300,
well I am little to fast to get critical when things dont work.

I found some linux stuff (.h files, .so files, python, etc) still looking
for the c compiler, (on the microdrive).

if the EDK 'obsoleted' TFT is 'supposed' to work, I will give it a try.
no problems.

and montavista, guess it makes sense to ask for ver 3.0
ml300 microdrive has 2.1 Professional installed.

thanks,
and I do my homework better now
e.g. when attempt to start c compiler on linux I will not yiell
that C compiler isnt there (in 5 minutes) but keep searching
for the compiler. ok, search is in progress :)


Peter Ryser <ryserp_at_xilinx.com> wrote in message news:<3F036954.D30250BE_at_xilinx.com>...
Quote:
Antti,

the Linux demo shipping with ML300 comes with X Windows and a ton of servers
and applications. If for some reason your board came with just a very simple
command line version of Linux you can get the full MicroDrive image from the
ML300 lounge accessible from http://www.xilinx.com/ml300.

If you want to start your own development with Linux on Virtex-II Pro please
contact MontaVista and ask them for MontaVista Linux 3.0 for ML300. They will
be able to give you more information on the content and the pricing of their
product.

V2PDK is still supported by Xilinx. However, it is in the process of being
replaced with EDK. The V2PDK design for the ML300 is currently ported over to
V2PDK and you should be able to download it from the ML300 lounge in the near
future. A first version of the port will not support all peripherals that
have been available in V2PDK but will give enough functionality to boot
Linux.

The TFT in EDK works as it is the same as in V2PDK.


tk
Guest

Fri Apr 21, 2006 10:49 pm   



hi antti,

seems good for you : )

i just download compiled programs from a Linux PC to the ML300 (microdrive)
through network

i'm sure the built-in embedded Linux demo has full network support
just plug in the network cable and it will be ok !!

cheers,

tk

"Antti Lukats" <antti_at_case2000.com> wrote in message
news:80a3aea5.0307040020.222ea437_at_posting.google.com...
Quote:
"tk" <tokwok_at_hotmail.com> wrote in message
news:<be09aq$804$1_at_hkueee5.eee.hku.hk>...
Hi,

I've written a very simple application (hello world Smile for the Linux in
ML300 using
ELDK's ppc_4xx cross compiler.

http://lists.linuxppc.org/linuxppc-embedded/200305/msg00033.html

I think it will be great if Xilinx can issuse some reference about how
the
Linux demonstrating platform can be built. It will be useful for
building
a customerized embedded Linux platform.

hi tk,

well xilinx just promised that an EDK project capable of minimal
linux boot will be made (available) - so at least there is hope.

I read your posting, but,,, I have no problems writing C programs
for ML300 and merging them with reference bitstreams, the results
also work :)

but to compile for the linux on microdrive, i would need to
1) get the header files
2) compile
3) copy the executable back
but the linux file system is so far unaccesible for me, eg
the microdrive seems to have hidden linux partition (not visible
on w2k host computer) and I havent managed to get the enet networking
so the microdrive linux works, but I have no means to get a compiled
program into it. ok, I need to plug in the network cable and see if
I get it running

antti


Kari Runk
Guest

Fri Apr 21, 2006 10:49 pm   



Mark Sandford wrote:
Quote:
Try http://www.Google.com

SP <nowhere_at_nowhere.com> wrote in message news:<Xns93ADB437CEF1nowherenowherecom_at_216.109.160.14>...

Hello,

I am looking for an ARM (preferably StrongARM) w/ FPGA development board.
StrongARM preference is for mainly for Linux. Any other supported processor
will do as well.

Thanks a lot!
-Sumeet


Take a look at Altera's Excalibur, it has ARM9 hard core + peripherals
and FPGA on the same die.

http://www.altera.com/products/devices/arm/kits/exc-dev_kits_boards.html

-KR-

Manfred Kraus
Guest

Fri Apr 21, 2006 10:49 pm   



I got a call from Insight. Of course I can get samples of the ESJ-part
immediately.
The Problem was, that I didn't ask for ESJ-Parts. They assumed I know what
to ask for.

Thanks to Peter for clarifying this.

-Manfred Kraus

mkraus_at_cesys_dot_com

Uwe Bonnes
Guest

Fri Apr 21, 2006 10:49 pm   



Manfred Kraus <news_at_cesys.com> wrote:
: I got a call from Insight. Of course I can get samples of the ESJ-part
: immediately.
: The Problem was, that I didn't ask for ESJ-Parts. They assumed I know what
: to ask for.

The problem is also, that distributors often ask for an exact number, while
the user mostly needs _any_ part with only few constraints. That way, you
have to prepare a lot of fallback fits, and ask the distributor for each.

If they could cope with wildcards in the part number, things would be
easier...

Bye
--
Uwe Bonnes bon_at_elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Rene Tschaggelar
Guest

Fri Apr 21, 2006 10:49 pm   



Rene Tschaggelar wrote:
Quote:

There is no SOPCBuilder as it should be according to the pdf.
I browswed the SOPC Builder solutions in the knowledge base.

Thanks this far for the messages.

The SOPC builder appears to be correctly installed.
There is no java running, at least it was not detectable.
The is no other cygwin either.

From the taskmanager it appears the perl.exe is somehow failing.
It comes upon the SOPC button and goes right away.

Rene
--
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net

tk
Guest

Fri Apr 21, 2006 10:49 pm   



so good that Xilinx sent you the example
i'm interested in it, can u send me (email: h0013252_at_eee.hku.hk) a copy ?

i'm now finding out how to build (glue all the IP cores needed) an embedded
system environment for the MontaVista Linx (Pro 3.0) to work on, do you
know any reference about that (so as to build an embedded Linux similar
to the one on ML300) ?


Quote:
I can ping from ml300/linux, start FTP to location outside our network
but thats not very comfortable using commandline ftp on ml300 and 3rd
party ftp server as intermediate mailbox to copy files is not fun.

for my case, it's rather convenient for me, i just mount a network drive
from
other Linux PC on ML300/Linux

seems that thare are programs running under M$ Windows can access
Linux partition

but i will suggest you put the files in the FAT partition, then access the
files
in Linux by mounting the FAT partition (it's "/dev/xsysace/disc0/part1" in
my
case)

cheers,

tk


"Antti Lukats" <antti_at_case2000.com> wrote in message
news:80a3aea5.0307040614.743f3071_at_posting.google.com...
Quote:
hi antti,

seems good for you : )

i just download compiled programs from a Linux PC to the ML300
(microdrive)
through network

i'm sure the built-in embedded Linux demo has full network support
just plug in the network cable and it will be ok !!


lucky you! there are no linux PCs in our office and a corporate router
may filter some stuff out, so plugging in, doesnt work 100%

I can ping from ml300/linux, start FTP to location outside our network
but thats not very comfortable using commandline ftp on ml300 and 3rd
party ftp server as intermediate mailbox to copy files is not fun.

our network gurus know almost nothing about linux etc, well work in
progress

what is good news that I did receive a working example for EDK incl

DDR (and ethernet) - so web server from that example does work and
I can access it from corporate network also.

too bad the microdrive linux partition is not accessible at all Sad
it is there I know, 800MB are vanished (drive properties says 200MB
for 1GB microdrive)

tnx for help
antti


Leon Heller
Guest

Fri Apr 21, 2006 10:49 pm   



"juice28" <jstancliff_at_mchsi.com> wrote in message
news:GaZMa.29717$fG.15119_at_sccrnsc01...
Quote:
Version 5.2 only works on windows 2000. I am using 3.2 as it seems to be
the only one that works on my setup. I have also assigned the input and
outputs to pins using the user constraints, but I did not use the ibuf and
obuf (it seemed to compile alright though) so maybe that is my problem.
Still wondering what is up with Q/ on the flip flops too.


You have to add an inverter.

Leon
--
Leon Heller, G1HSM
leon_heller_at_hotmail.com
http://www.geocities.com/leon_heller

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