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Eric Crabill
Guest

Fri Apr 21, 2006 10:49 pm   



Hi,

There are a number of boards available. You should look
for a server class motherboard, one that supports PCI-X
or at least PCI at 66 MHz. A board that supports either
of those will be (by requirement) at 3.3v slot, not a 5.0v
slot.

If you are looking for a cheap machine that will do the
job, you may consider the HP Kayak XU800. I see a number
of them available on Ebay from time to time.

Eric

Colin Hall wrote:
Quote:

Dear All,

Apologies if this is slightly off-topic but I hope there may be
someone reading who has faced a similar problem.

I have a prototype 33/32 PCI peripheral. The PCI bus interface is
implemented in a Spartan-IIE device, which is not +5V tolerant. Design
verification of the hardware is underway on this new design.

I would like to make progress on software development while we wait
for the hardware to be finished. To that end, I am looking for a
PC-architecture motherboard into which I can plug our prototype card
without blowing the Spartan-IIE device.

I tried searching for suitable commodity motherboards. There are
plently of boards but none of them specified that their PCI bus
interfaces were 3.3V only.

If anyone can suggest a suitable board I would be most grateful.

Regards,
Colin.


M.Randelzhofer
Guest

Fri Apr 21, 2006 10:49 pm   



"Peter Alfke" <peter_at_xilinx.com> schrieb im Newsbeitrag
news:3F01C8E9.9E79F922_at_xilinx.com...
Quote:
Let's stick with English, otherwise we have ro rename this the
"FPGAinformationsaustauschzentralverteilungsstelle".

OK, but i didn't know that this NG is called
"FPGAinformationexchangecentraldistributioncenter".

Quote:

All presently existing S3-50s lack the BlockRAM and therefore the DLLs (
BlockRAM and DLL share a column. When we took out one, we had to take
out the other). The decision was made in order to speed up the design,
and was then reversed, so all future production 50's will have BlockRAMs
and DLLs.

So the present s3-50 devices without blockrams are the fastest s3 90nm chips
forever ?

MIKE

Luiz Carlos
Guest

Fri Apr 21, 2006 10:49 pm   



Quote:
You can feel how you wish about your designs, but even the loss of the
64 bit dual ports and the 128 bit single port rams is not signficant.
To make a 64 bit dual port RAM requires 8 LUTs for ram (same as in VII)
and one LUT for the read mux and possibly two more LUTs for the WEs.
But if this is part of a larger ram block you are making half of the WEs
would have been required anyway. So it is not a "large" amount of
logic, just a bit more.

Ok, I agree with you, itīs not to much logic. But because these extra
delays maybe I have to duplicate the circuits.

Quote:
If you are making really large blocks where the longer runs on the
address and data can slow it down significantly, then you likely are
better off with the block rams.

No, they are not large blocks, but I have 128 to 512 FIR filters (256
coefs) running in parallel, and the sampling rate is 2 megaHertz.
Throughput!

Quote:
Considering the much lower price of the XC3S parts, all this sounds to
me like a benefit, not a liability. Think of it as paying for the LUTs
that have RAM and getting the other LUTs for free Smile

I'm not complaining, and I know that Xilinx wil not make a special
Spartan3 just for me. But I have the right to express what I think,
and maybe I'm not alone. Maybe there are a lot of Luizes and Rays,
maybe Xilinx will hear us and maybe, at these nanometer scales where
the pads are so big, to have all the CLBs configurable as memory is
not so significant in silicon area.

Luiz Carlos Oenning Martins
KHOMP Solutions

Subroto Datta
Guest

Fri Apr 21, 2006 10:49 pm   



already5chosen_at_yahoo.com (Michael S) wrote in message news:<f881b862.0307010229.563153f_at_posting.google.com>...
Quote:
sdatta_at_altera.com (Subroto Datta) wrote in message news:<ca4d800d.0306301212.1cd9be9c_at_posting.google.com>...
already5chosen_at_yahoo.com (Michael S) wrote in message news:<f881b862.0306300619.58b3f8a5_at_posting.google.com>...
Following PLL was generated with MegaWizard Plug In Manager and
compiled (for Stratix) under Quartus 2.2:
Input Frequency: 36MHz
Dynamic reconfiguration is in use.
c0 Clock Multiplication Factor = 158
c0 Clock Division Factor = 36
Other counters are not in use.
The compilation report shows:
M value = 79
N value = 3
VCO frequency = 948MHz !!!!
It looks like Quartus design team is not aware of limitations of the
Stratix PLL as listed in the respective datasheet (300 to 800MHz for
-5 and -6 grades, 300 to 600MHz for -7 grade). They live under
impression that everything up to 1000MHz is o.k. Sad
The Stratix Fast PLL can go up to 1GHz for certain speedgrades, which
is why the Megawizard allows this (only the Enhanced PLL is limited to
800Mhz). A design that needs a VCO at 1GHz will work in Stratix. The
PLL will then be placed on the Fast PLL and be used as a general
purpose PLL. However a Fast PLL cannot be used for dynamic
reconfiguration, and this should have been reported during fitting.

For Quartus II version 3.0, the Megawizard has been enhanced to
recognize that only an Enhanced PLL can be used when dynamic
reconfiguration is selected, and as a result it will ensure that the
VCO is valid for an Enhanced PLL in the Megawizard itself. The
Megawizard will become speedgrade aware in a future release of
Quartus. In the meantime all calculations are based on the fastest
speedgrade.

- Subroto Datta
Altera Corp.



I don't have Quartus II version 3.0 (BTW, is it already available ?)
so can't comment about it. What I do know - Quartus II version 2.2
Megawizard doesn't emit "enhanced" set of PLL parameters, so the
Megawizard has no direct control of the VCO frequency. Unless it was
changed in the 3.0, I can't see how improvements in the Megawizard
would fix the problem. IMHO, the bug is in the compiler and it's where
it should be fixed.
In the mean time, the only reliable solution I can think of is:
1. Don't use the Megawizard.
2. Manually set enhanced parameters for the altpll().
It would work, of coarse, but it's a PITA...

Regards,
Michael


In Stratix devices there are two types of PLLs - Enhanced PLLs and
Fast PLLs. The Megawizard performs a feasibility check to make sure
the resulting parameters the compiler will compute (including the VCO
frequency) will be valid for at least one of these PLL types. For
Quartus II 3.0, the Megawizard is aware of the restriction that forces
the use of Enhanced PLLs when using reconfiguration, and as a result
will make sure all parameters can be implemented in an Enhanced PLL
earlier on in the flow.

But even in Quartus II 2.2, the compiler will give an error if the PLL
cannot be implemented in either of the PLL types, including if no set
of internal parameters could achieve the requested PLL settings and a
legal VCO for the speed grade selected. If a legal set of internal
parameters did exist that could achieve the requested PLL settings,
then the compiler will implement those parameters.

Quartus II 3.0 was released to production/manufacturing on June 27th
so you should be seeing it real soon.

- Subroto Datta
Altera Corp.

Uwe Bonnes
Guest

Fri Apr 21, 2006 10:49 pm   



Mike Randelzhofer <michael.randelzhofer_at_mchf.siemens.de> wrote:

: Hab auch ein paar S3-50 in der Schublade...
: Weiss aber immer noch nicht ob die Blockrams und DLL's haben oder nicht ?

: Gruss MIKE

: for our english readers:
: I also have some spartan3-50 devices, but don't know if they have blockrams
: and dll's ?

To my knowledge, the first batch of 3S50 was made without BRAM and DLLs. Try
to decipher the Date Code and you probably you'll find information on the
Xilinx webpage ( and you probably will get feedback here).

Bye
--
Uwe Bonnes bon_at_elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Peter Alfke
Guest

Fri Apr 21, 2006 10:49 pm   



"M.Randelzhofer" wrote:
Quote:

So the present s3-50 devices without blockrams are the fastest s3 90nm chips
forever ?

No, when I wrote "speed up", I meant weeks in design, not picoseconds in operation.
Spartan3 is not the fastest, in some areas it is slower than Virtex-II,
since the priorities for Spartan3 were: 1. low cost, 2. low cost, and 3.
low cost. We don't throw away speed, but we did not increase the chip
size to gain performance.
Deleting BRAM and DLL does nothing to the performance, but it reduced
the design effort, and it made the chip smaller. But this is all history now.

"FPGAinformationsaustauschzentralverteilungsstelle" was meant as a joke,
referring to the American fascination with the German capability to
concatenate words ad infinitum. Donaudampfschifffartgesellschaftskapitaen....

Peter Alfke



Peter Alfke

Peter Ryser
Guest

Fri Apr 21, 2006 10:49 pm   



Please make sure that you are using the latest Xilinx Implementation tools.
From the previous message I can see that you are using 5.1. The latest
tools are 5.2i with service pack 3.

When looking at the schematics for the ML300 you will see that the FPGA
PROG button goes to the corresponding pin on the FPGA, i.e. pushing the
button will clear out the contents of the FPGA.

- Peter




tk wrote:

Quote:
Hi all,

I have problem in configuring the xc2vp7 on the ML300 board. The
problem is described in the previous thread "ERROR:iMPACT:583".

I doubt that I have omitted some settings on the ML300 board during
programming (or have done sth wrong in iMPACT). There is a button
called "FPGA PROG" on the ML300 board. I've searched through the
documentation but I couldn't find out what's it for.

Does anyone have the experience on using ML300 that can share with me ?

Thanks very much.

tk


Steven K. Knapp
Guest

Fri Apr 21, 2006 10:49 pm   



"rickman" <spamgoeshere4_at_yahoo.com> wrote in message
news:3F00FDD2.C74022BD_at_yahoo.com...
Quote:
"Nicholas C. Weaver" wrote:
That is a good point about the tools. I forget that the XC3S is only
supported in webpack in the XC3S50 now and I think only up to the
XC3S400 in the next release. I honestly don't get the idea of selling
very low cost chips and not adding them to the free tools.

Personally, I agree with your statement and have been trying to convince the
powers that be to add additional Spartan-3 devices to WebPack. The folks
responsible for WebPack are concerned about the total download size. The
larger devices have multi-MB support files.

Quote:
But good luck getting a price on the XC3S1000 at this point. The
XC3S1000 parts have been pushed back due to design problems and will not
be out until Q1 or perhaps later. The XC3S400 and one of the larger
parts will be out in 4Q03 according to their schedule.

Hmm. Engineering samples of the XC3S1000 and XC3S50 are available today.
The engineering samples have the part number XC3S1000J and XC3S50J to
distinguish them from the production devices. This may be the reason you
were quoted longer delivery. The non-'J' devices are due out in 4Q2003.
The non-'J' version of the XC3S50 also includes block RAM, embedded
multipliers, and 2 Digital Clock Managers (DCMs), which the XC3S50J does
not.


--
---------------------------------
Steven K. Knapp
Applications Manager, Xilinx Inc.
General Products Division
Spartan-3/II/IIE FPGAs
http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Spartan-3
Tel: (408) 626-7447
E-mail: steve.knapp_at_xilinx.com
---------------------------------

Jim Granville
Guest

Fri Apr 21, 2006 10:49 pm   



Steven K. Knapp wrote:
Quote:

"rickman" <spamgoeshere4_at_yahoo.com> wrote in message
news:3F00FDD2.C74022BD_at_yahoo.com...
"Nicholas C. Weaver" wrote:
That is a good point about the tools. I forget that the XC3S is only
supported in webpack in the XC3S50 now and I think only up to the
XC3S400 in the next release. I honestly don't get the idea of selling
very low cost chips and not adding them to the free tools.

Personally, I agree with your statement and have been trying to convince the
powers that be to add additional Spartan-3 devices to WebPack. The folks
responsible for WebPack are concerned about the total download size. The
larger devices have multi-MB support files.

You could always shock them with the 'left field' concept of selective
downloading just the device library files you need ? :)

-jg

rickman
Guest

Fri Apr 21, 2006 10:49 pm   



Peter Alfke wrote:
Quote:

rickman wrote:


Except that I often am contacted by Altera directly rather than here in
public. I can understand why they would do that.

I cannot understand that at all. If the question is ventilated in
public, it should be answered in public. Unless the answer is very embarrassing...

Peter Alfke, Xilinx

Often vendors don't want to seem like they are hawking their wares
here. So I see nothing wrong with contact on a more personal level in
order to get a good answer to a question. When your sales people make
calls on customers, they don't invite the competition to come along do
they? Support is no different. Why should the open the door for
kibitzing from the competition? And maybe they will be revealing some
information that they don't want the competition to have. I know that
Xilinx has been pretty tightlipped about their product schedules. At
least I have had a very hard time getting that info until a couple of
weeks ago when I insisted that I needed it on the Spartan 3s.

--

Rick "rickman" Collins

rick.collins_at_XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

rickman
Guest

Fri Apr 21, 2006 10:49 pm   



Luiz Carlos wrote:
Quote:

You can feel how you wish about your designs, but even the loss of the
64 bit dual ports and the 128 bit single port rams is not signficant.
To make a 64 bit dual port RAM requires 8 LUTs for ram (same as in VII)
and one LUT for the read mux and possibly two more LUTs for the WEs.
But if this is part of a larger ram block you are making half of the WEs
would have been required anyway. So it is not a "large" amount of
logic, just a bit more.

Ok, I agree with you, itīs not to much logic. But because these extra
delays maybe I have to duplicate the circuits.

If you are making really large blocks where the longer runs on the
address and data can slow it down significantly, then you likely are
better off with the block rams.

No, they are not large blocks, but I have 128 to 512 FIR filters (256
coefs) running in parallel, and the sampling rate is 2 megaHertz.
Throughput!

Considering the much lower price of the XC3S parts, all this sounds to
me like a benefit, not a liability. Think of it as paying for the LUTs
that have RAM and getting the other LUTs for free :)

I'm not complaining, and I know that Xilinx wil not make a special
Spartan3 just for me. But I have the right to express what I think,
and maybe I'm not alone. Maybe there are a lot of Luizes and Rays,
maybe Xilinx will hear us and maybe, at these nanometer scales where
the pads are so big, to have all the CLBs configurable as memory is
not so significant in silicon area.

Yes, certainly you have the right to express your views and to let
Xilinx know what you need. But I think you are responding to the idea
that "something" is missing without knowing for sure if it is really an
issue. When you say above that adding the level of logic may slow down
the design, you first need to know how fast these parts run. After all,
you are comparing 90 nm Spartan 3s to 150 nm VirtexIIs. It is very
possible that the S3s will run faster even with the added delays.

I am sorry if my "nagging" is annoying. But I have watched a lot of
changes in FPGAs and have often felt they were not for the better. But
somewhere around the Virtex or VirtexII parts I started to realize that
I needed to forget about how the parts were different and focus on how
to solve my design problems using them. With that I have come to
understand that often what I saw as a limitation is more than made up
for in other areas. I am sure that Xilinx does not remove functionality
without considering the trade offs very seriously.

--

Rick "rickman" Collins

rick.collins_at_XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

rickman
Guest

Fri Apr 21, 2006 10:49 pm   



Peter Alfke wrote:
Quote:

Xilinx has two major product lines. Virtex is for performance and
features, Spartan is for low cost. Otherwise, the architectures are very similar.

That gives us a chance to really optimize each line. The Spartan
developers reduce the cost, accepting that this makes their devices
non-optimal for certain applications, but there is always Virtex to
deliver higher functionality and performance (at a higher price).
The Virtex designers can optimize functionality and speed, knowing that
this might increase the cost, but there is always Spartan to satisfy
less performance-critical, but more cost-sensitive applications.

There is no free lunch, in engineering almost everything is a trade-off.
But everybody still asks for champagne on a beer budget Smile
Peter Alfke

I am not looking for champagne on a beer budget, but I would sure like
to be able to pour them both into the same glass. That is I would like
to have one footprint that I an put a Spartan into for low cost or a
Virtex when I need high performance and large size.

--

Rick "rickman" Collins

rick.collins_at_XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

rickman
Guest

Fri Apr 21, 2006 10:49 pm   



"Steven K. Knapp" wrote:
Quote:

"rickman" <spamgoeshere4_at_yahoo.com> wrote in message
news:3F00FDD2.C74022BD_at_yahoo.com...
"Nicholas C. Weaver" wrote:
That is a good point about the tools. I forget that the XC3S is only
supported in webpack in the XC3S50 now and I think only up to the
XC3S400 in the next release. I honestly don't get the idea of selling
very low cost chips and not adding them to the free tools.

Personally, I agree with your statement and have been trying to convince the
powers that be to add additional Spartan-3 devices to WebPack. The folks
responsible for WebPack are concerned about the total download size. The
larger devices have multi-MB support files.

If the size of the download is the issue, there are very simple ways to
address that. One is to split the download into two parts, one for the
current configuration and one for the added support for the larger
devices. The other is just to ship the CD as you already do. I don't
think adding all the chips will blow away a CD will it? As it is, I
don't think it is very practical to ask a user to download a 150 MB
file. At least it is not practical for me to download it.


Quote:
But good luck getting a price on the XC3S1000 at this point. The
XC3S1000 parts have been pushed back due to design problems and will not
be out until Q1 or perhaps later. The XC3S400 and one of the larger
parts will be out in 4Q03 according to their schedule.

Hmm. Engineering samples of the XC3S1000 and XC3S50 are available today.
The engineering samples have the part number XC3S1000J and XC3S50J to
distinguish them from the production devices. This may be the reason you
were quoted longer delivery. The non-'J' devices are due out in 4Q2003.
The non-'J' version of the XC3S50 also includes block RAM, embedded
multipliers, and 2 Digital Clock Managers (DCMs), which the XC3S50J does
not.

I have been told that the 50 and 1000 have a design problem with 3 volt
tolerance and have been pushed back from late Q3 or early Q4 to 1Q04.
The other two or three chips due out in Q4 (including the XC3S400) are
now the first chips to be available in full production.

I am having a lot of trouble getting straight information and this is
what I currently have in print! If this is not correct, I really need
to know now!

--

Rick "rickman" Collins

rick.collins_at_XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

Paul Leventis
Guest

Fri Apr 21, 2006 10:49 pm   



Hi Marc,

Quote:
I love competitive comparisons, and I love Altera for continuing to
push the level of competition higher, but PLEASE, could you keep this
FUD free?

Interesting... I thought my posting was relatively FUD free. Have I have
been on the dark side for too long? :-)

Quote:
Xilinx tells everybody that the speed files that are released for the
Spartan-3 are very preliminary and quite conservative, and I'm sure
your tech people know that.

I am a tech person... I assure you that we're the last customer of ISE that
Xilinx cares to inform about future performance!

The software is the silicon -- it doesn't matter how fast the chip is if you
don't know how fast your design will run on it. I would be leary of relying
on a nebulous future performance improvement; I think the performance
reported *today* is very relevant for people making decisions today.
Besides, in postings to this newsgroup at least, Xilinx has indicated that
they sacked performance in order to reduce costs. So how conservative is
the timing? 5%? 10%? 100%? I don't know. Do you?

Quote:
This is bordering on the same level of
FUD that I got from my Altera rep about some Virtex II availability or
yield or some such nonsense early this year.

Hmm... I'd go listen to some Xilinx conference calls from the same time
period, and look at recent dielectric decisions on VIIPro, and look at when
products shipped vs. dates indicated in announcements before proclaiming
that FUD.


Quote:
All of these would be better talking points than some nebulous claim of
being
30% faster than a part that is nowhere near released and whose claimed
speed is known to be artificially low.

I guess it's not that fair for me to compare a released, available, fully
characterized product with a final timing model against a product that is
barely sampling. But that is what the original poster was asking for, and
that's all I can compare against. And the "nebulous" claim was 20% faster
(slowest Cyclone to only Spartan 3 speed grade), or ~55% for the fastest
Cyclone speed grade. These are not "up to" numbers -- they are geometric
averages over 50+ user designs.

Have yourself a great long weekend,

Paul Leventis
Altera Corp.

Greg Steinke
Guest

Fri Apr 21, 2006 10:49 pm   



Rick,
On your question on startup current - I don't know this offhand but
will track this down with the hotline guy, as we don't want to
duplicate effort.

The other question about quiescent current:
Your interpretation is correct. The 5 mA value applies to -2 and -3
commercial-temp devices and -3 industrial/extended-temp devices, while
the 10 mA value applies to -1 commercial-temp devices and -2, -3
industrial/extended-temp devices. The spec applies to a configured
part with no toggling inputs. We do not have a spec for the
unconfigured part. In reality it may be slightly higher, but not much
more.

Greg Steinke
Altera Applications
gregs_at_altera.com


rickman <spamgoeshere4_at_yahoo.com> wrote in message news:<3F047811.D824824C_at_yahoo.com>...
Quote:
Since Altera seems to be active in this group, I will ask the question
here. I have finally gotten an acceptable price on the EP1K30 part (5
volt tolerant) and will be using it in my design provided I don't step
on any landmines looking at the data sheet in fine detail. One item
that is missing is the startup current. I called support and got a
number of 194 mA. But I asked if this was over temp and voltage and he
didn't know. He said he would dig up the answer and get back to me
which never happened.

So who can tell me the power-up current for the EP1K10, EP1K30, EP1K50
and EP1K100 in both commercial and industrial temp grade over
temperature and voltage?

Also, I am not certain I understand the quiescent current spec on this
part. There are two values, one has a footnote...

ICC0 VCC supply current (standby)

(12) This parameter applies to -1 speed grade commercial temperature
devices and -2 speed grade industrial and extended temperature devices.

Does this mean the lower value (5 mA) without the footnote applies to
all other devices?

Am I correct in assuming that this spec is for a configured part with no
clock as well as an unconfigured part?

--

Rick "rickman" Collins

rick.collins_at_XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX


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