EDIF file /netlist for FPGA

Fri Jul 18, 2003 11:02 pm   

Good evening,

Does anybody have an EDIF file after synthesis for FPGA : I would like to
see what it looks like for an example ?
And which cad software could read it ?

Thanks in advance,

Vi

Sat Jul 26, 2003 1:18 am   

I can give you a sample edif file synthesised using Xilinx's tools.
However I need to know what use you will put it to. This edif
file can be read using either Xilinx's Place and Route tools
or other simulation tools which can accept netlist in edif format.

Thanx,
Ab.