elektroda.net NewsGroups Forum Index - FPGA - DONE_cycle:6 setting neccessary in bitgen
Gabor
Guest
Guest
Thu Feb 11, 2010 10:35 pm
On Feb 11, 2:50 pm, van...@sfu.ca (Peter Van Epp) wrote:
Quote:
snip>>And another question is: what else did the assembly house mess up on
this board? Lot of 0402 bird seed on this one, no way to tell by looking
at it... But at least all supply voltages are correct and so on.
snip
This reminded me of an article I saw in Circuit Cellar on Smart Tweezers
(http://www.smarttweezers.com) which might help you out. I expect there may
be some problems in circuit with parallel paths though, I think it is more
meant for identifying mystery components in isolation.
Peter Van Epp
this board? Lot of 0402 bird seed on this one, no way to tell by looking
at it... But at least all supply voltages are correct and so on.
snip
This reminded me of an article I saw in Circuit Cellar on Smart Tweezers
(http://www.smarttweezers.com) which might help you out. I expect there may
be some problems in circuit with parallel paths though, I think it is more
meant for identifying mystery components in isolation.
Peter Van Epp
We've got a set of these in our production area here, which is also
the test and rework area (small company). You can often get
information
in-circuit, especially in cases like this where you might see a much
lower
impedance than you were expecting. They're also great for comparing
two boards when one doesn't work, since whatever you measure on the
good board (R L or C) is just a relative reference point rather than
the presumed component value.
Regards,
Gabor
Brian Davis
Guest
Guest
Fri Feb 12, 2010 4:31 am
Sean Durkin wrote:
Quote:
snip> clamping the DONE voltage seen at the FPGA pin to one
VBE drop such that the FPGA thinks DONE never went high.
Ha, THAT was it! Thank you, you made my day! Putting in the
right value fixes the issue: Bit-files load without the
DONE_cycle-setting, plus indirect SPI-programming works now.
Great! I hadn't seen that exact problem before, but the DONE LED
circuit found on many Xilinx/Digilent boards made me think of it:
:
: !!! Don't ever do this !!!
: Evil circuit clamps DONE high level to the LED's Vf
:
: DONE >---o---/\/\---> VCC
: |
: |
: v
: - LED
: |
: |
: GND
Given that most Xilinx FPGAs have a Vih minimum threshold on
the DONE pin of 2.0 V (LVTTL, LVCMOS33) or 1.7 V (LVCMOS25),
it gives me the heebie-jeebies to see a circuit like that
clamping DONE to the LED Vf - depending upon the exact LED,
Vf could easily be down in the 1.5 V to 1.7 V range.
Quote:
The only question that remains is: why doesn't iMPACT give
a "DONE did not go high"-message? If it did, I'd probably
gotten there sooner.
There are two DONE related bits in the V5 status register,
an internal "I-have-released-done" signal and then the actual
DONE pin state; I'd guess that iMPACT is reading the former.
The FPGA startup state machine uses the external signal seen
on the DONE pin, so the FPGA will stall the startup sequence
with your accidental Vbe clamp on DONE.
It would be interesting to compare the before and after
board-resistor-change state of the status register
[Debug->Read Device Status], post JTAG download attempt.
There are other helpful bits in that status register for
troubleshooting exactly where the FPGA got stuck, here's a few:
"
" STARTUP_STATE [20:18] CFG startup state machine [ NOT BINARY
ENCODED!!!]
" DONE [14] Value on DONE pin
" RELEASE_DONE [13] Value of internal DONE signal
" EOS [4] End of Startup signal from Startup Block
"
from UG191 v3.8, V5 FPGA Configuration guide, page 120:
http://www.xilinx.com/support/documentation/user_guides/ug191.pdf
Quote:
Antti did post his version of such a core in the Xilinx user
forums, though:
http://tinyurl.com/yjtharz
Thanks, I hadn't seen that one before.
Brian
Peter Van Epp
Guest
Guest
Fri Feb 12, 2010 4:50 am
Gabor <gabor_at_alacron.com> writes:
Quote:
On Feb 11, 2:50=A0pm, van...@sfu.ca (Peter Van Epp) wrote:
snip>>And another question is: what else did the assembly house mess up =
on
this board? Lot of 0402 bird seed on this one, no way to tell by looking
at it... But at least all supply voltages are correct and so on.
snip
=A0 =A0 =A0 =A0 This reminded me of an article I saw in Circuit Cellar on=
Smart Tweezers
(http://www.smarttweezers.com) which might help you out. I expect there m=
ay
be some problems in circuit with parallel paths though, I think it is mor=
e
meant for identifying mystery components in isolation.
Peter Van Epp
We've got a set of these in our production area here, which is also
the test and rework area (small company). You can often get
information
in-circuit, especially in cases like this where you might see a much
lower
impedance than you were expecting. They're also great for comparing
two boards when one doesn't work, since whatever you measure on the
good board (R L or C) is just a relative reference point rather than
the presumed component value.
Regards,
Gabor
snip>>And another question is: what else did the assembly house mess up =
on
this board? Lot of 0402 bird seed on this one, no way to tell by looking
at it... But at least all supply voltages are correct and so on.
snip
=A0 =A0 =A0 =A0 This reminded me of an article I saw in Circuit Cellar on=
Smart Tweezers
(http://www.smarttweezers.com) which might help you out. I expect there m=
ay
be some problems in circuit with parallel paths though, I think it is mor=
e
meant for identifying mystery components in isolation.
Peter Van Epp
We've got a set of these in our production area here, which is also
the test and rework area (small company). You can often get
information
in-circuit, especially in cases like this where you might see a much
lower
impedance than you were expecting. They're also great for comparing
two boards when one doesn't work, since whatever you measure on the
good board (R L or C) is just a relative reference point rather than
the presumed component value.
Regards,
Gabor
Even better, someone that has actually used one (which I haven't
).
Peter Van Epp
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