Does VHDL support standard probability distributions

Mon Dec 14, 2009 8:15 am   

Could some VHDL guru please help ? I am trying to generate a jittery
clock pulse e.g., clock pulses with pulse width jitter distributed in
an uniform distribution, within pre-defined upper and lower bounds,
e.g., something similar to $dist_uniform in Verilog. Any hints
suggestions would be of immense help.
Thank you.

Mon Dec 14, 2009 10:57 am   

On Sun, 13 Dec 2009 22:15:46 -0800 (PST), Daku wrote:


use ieee.math_real.all;
.....

process
variable seed1, seed2: integer;
variable rnd: real;
begin
seed1 = ...;
seed2 = ...;
while ... loop
uniform(seed1, seed2, rnd);
--- rnd now contains a value uniformly distributed over 0.0:1.0
end loop;
...

I have a vague recollection of seeing some derived distribution
functions (poisson, gaussian etc) on the net, but I never checked
them out in detail and Google will work as well for you as for me.
Otherwise, ieee.math_real.uniform() is what you get - and, of
course, some custom code to massage the distributions.

Don't touch the seed variables - just prime them with some
value, and leave them alone for the uniform() procedure to
work on.
--
Jonathan Bromley

Mon Dec 14, 2009 12:43 pm   

Jonathan Bromley <jonathan.bromley_at_MYCOMPANY.com> writes:


Clearly one of the them should be initialised to '42', but what about
the other one :)

Cheers,
Martin

--
martin.j.thompson_at_trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html

Mon Dec 14, 2009 12:53 pm   

On Mon, 14 Dec 2009 11:43:51 +0000, Martin Thompson wrote:


O frabjous day - someone else who initialises his seeds correctly!
Since 42 is the answer to "what is six nines", the correct second
seed value plainly should be 54 to maximise random stability.
--
Jonathan Bromley