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Does the parameter 'width' take effect in the called module?

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elektroda.net NewsGroups Forum Index - Verilog Language - Does the parameter 'width' take effect in the called module?

Robert Willy
Guest

Mon Feb 05, 2018 12:45 am   



Hi,
I am still new on Verilog when I read the below code, which is downloaded
from the web. 'width' is a parameter of the CIC filter wordlength. I think
the width is 18, as '18' in CIC_tb overwrite '12' in CIC module.

When I simulated in Modelsim, I want to increase the CIC module width from
18 to 20. I find that Modelsim only shows CIC_tb is modified. I can only
compile CIC_tb to get the project updated (without compiling CIC). This
puzzles me a lot, as I don't think CIC module can automatically be updated
to width 20 with only parameter in CIC_tb.v changed.

Can you explain it to me?


Great thanks to you.










////////////
module CIC_tb;
reg clk;
reg rst;
reg [15:0] decimation_ratio;
reg signed [7:0] d_in, d_in0;
wire signed [7:0] d_out;
wire d_clk;

integer x_in, x_read, x_out;

CIC #(.width(1Cool) CIC(.clk(clk),
.rst(rst),
.decimation_ratio(decimation_ratio),
.d_in(d_in),
.d_out(d_out),
.d_clk(d_clk));


always #1 clk = ~clk;

always @(posedge d_clk)
begin
$fwrite(x_out,"%d\n",d_out);
end

initial
begin
clk <= 1'b0;
rst <= 1'b0;
decimation_ratio <= 16'd4;
d_in <= 13'b0;
d_in <= 40;
tmp <= 1'b0;
x_in <= $fopen("x.txt","r");
x_out <= $fopen("x_out.txt","w");
end
....

module CIC #(parameter width = 12)
(input wire clk,
input wire rst,
input wire [15:0] decimation_ratio,
input wire [7:0] d_in,
output reg signed [7:0] d_out,
output reg d_clk);

reg signed [width-1:0] d_tmp, d_d_tmp;

Gabor
Guest

Mon Feb 05, 2018 4:32 am   



On Sunday, 2/4/2018 5:45 PM, Robert Willy wrote:
Quote:
Hi,
I am still new on Verilog when I read the below code, which is downloaded
from the web. 'width' is a parameter of the CIC filter wordlength. I think
the width is 18, as '18' in CIC_tb overwrite '12' in CIC module.

When I simulated in Modelsim, I want to increase the CIC module width from
18 to 20. I find that Modelsim only shows CIC_tb is modified. I can only
compile CIC_tb to get the project updated (without compiling CIC). This
puzzles me a lot, as I don't think CIC module can automatically be updated
to width 20 with only parameter in CIC_tb.v changed.

Can you explain it to me?

Great thanks to you.

////////////
module CIC_tb;
reg clk;
reg rst;
reg [15:0] decimation_ratio;
reg signed [7:0] d_in, d_in0;
wire signed [7:0] d_out;
wire d_clk;

integer x_in, x_read, x_out;

CIC #(.width(1Cool) CIC(.clk(clk),
.rst(rst),
.decimation_ratio(decimation_ratio),
.d_in(d_in),
.d_out(d_out),
.d_clk(d_clk));


always #1 clk = ~clk;

always @(posedge d_clk)
begin
$fwrite(x_out,"%d\n",d_out);
end

initial
begin
clk <= 1'b0;
rst <= 1'b0;
decimation_ratio <= 16'd4;
d_in <= 13'b0;
d_in <= 40;
tmp <= 1'b0;
x_in <= $fopen("x.txt","r");
x_out <= $fopen("x_out.txt","w");
end
...

module CIC #(parameter width = 12)
(input wire clk,
input wire rst,
input wire [15:0] decimation_ratio,
input wire [7:0] d_in,
output reg signed [7:0] d_out,
output reg d_clk);

reg signed [width-1:0] d_tmp, d_d_tmp;


I guess this may be confusion over what you expect compilation to do for
simulation. Certainly if you were to synthesize the code, CIC would
need to be re-synthesized for the new width. However for simulation,
it is possible for the simulator to consider a parameter as a
variable, similar to an argument for a software subroutine. This
of course would be a choice made by the simulation creator, and not
necessarily a feature of Verilog. Some other simulation platform
might want to recompile everything that depends on the parameter
in order to reduce simulation run time at the expense of some additional
compile time.

--
Gabor

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