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jr
Guest
Sun Jan 17, 2010 9:25 pm
hssig a écrit :
Quote:
I don't know, and it doesn't really matter in this moment.
Yes, it does matter because I am trying to find out whether it is
allowed to put the function "to_integer"
in the when trees of a case statement.
Nope. You can't have a non static computed value in a choice. The
compiler would have no means to determine if the case statement covers
each choice once and only once (think that the body of the function
might be not compiled yet).
You can use if/elsif instead.
--
jr
Particulier non cumulable
hssig
Guest
Sun Jan 17, 2010 9:57 pm
Quote:
I don't know, and it doesn't really matter in this moment.
Yes, it does matter because I am trying to find out whether it is
allowed to put the function "to_integer"
in the when trees of a case statement.
Cheers,
hssig
HT-Lab
Guest
Mon Jan 18, 2010 9:28 am
"hssig" <hssig_at_gmx.net> wrote in message
news:693daa5c-06aa-43e0-8b46-224383d7ba28_at_c29g2000yqd.googlegroups.com...
Quote:
Hi Jim,
when compiling such case description including the "to_integer"
function in the when-tree(s)
"when to_integer(cA) => ..."
Modelsim PE 6.5d (Compile Options 2008) also shows the warning: "Case
choice must be a locally static expression."
So if Mentor did implement the VHDL-2008 feature correctly there would
be no warning ?
Modelsim's VHDL2008 support is very limited, just look under
help->technotes->vhdl2008 to see what is currently supported (in 6.6),
Hans
www.ht-lab.com
Quote:
Cheers,
hssig
hssig
Guest
Mon Jan 18, 2010 9:30 am
Quote:
Others have spent time given you rational reasons for the restriction.
Yes, I agree. But at this point we are trying to find out if these
restrictions are still applicable for VHDL-2008 and whether M, X, A, L
or whatever vendors are implementing functions in case statements
the way the new standard is telling them.
Quote:
All I can tell you is that both Modelsim and Quartus disapprove.
This makes the reason irrelevant to me.
But that does not prove that they are implementing it correctly (or at
all), doesn't it ?
Cheers,
hssig
hssig
Guest
Mon Jan 18, 2010 2:51 pm
Hi Jim,
to get to the point: Before asking Lattice and Mentor I want to be
sure whether the following code should be warning-free or not
when compiling with VHDL-2008 option:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity function_in_case is
port( Clk : in std_logic;
Ad : in std_logic_vector(7 downto 0);
Sig : out std_logic_vector(1 downto 0)
);
end function_in_case;
architecture beh of function_in_case is
constant A : unsigned(7 downto 0) := x"00";
constant B : unsigned(7 downto 0) := x"01";
constant C : unsigned(7 downto 0) := x"EE";
signal addr : unsigned(7 downto 0);
begin
addr <= unsigned(Ad);
process(Clk)
begin
if rising_edge(Clk) then
case to_integer(addr) is
when to_integer(A) =>
Sig <= "00";
when to_integer(B) to to_integer(C) =>
Sig <= "01";
when others =>
Sig <= "11";
end case;
end if;
end process;
end beh;
Cheers,
hssig
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