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Disable/enable PSL assertions

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alb
Guest

Thu Jan 01, 1970 2:00 am   



Hi everyone [1],

I'm about to start some work with assertions on our Verilog-AMS
models. Unfortunately we have several tenths of models and not
all simulations scenarios require all assertions enabled all the
time, therefore I'd like to come up with some technique to be
able to enable/disable a set of assertions as needed.

First it came to my mind to use 'define' to enable/disable each
individual assertion but I find it tedious and difficult to
maintain.

Anyone out there having an idea? Any pointers?

Al

[1] this is cross-posted on comp.lang.verilog but the news editor
I'm currently using doesn't allow for setting the follow-up
field!


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HT-Lab
Guest

Sun Oct 22, 2017 12:26 pm   



On 21/10/2017 18:41, alb wrote:
Quote:

Hi everyone [1],

I'm about to start some work with assertions on our Verilog-AMS
models. Unfortunately we have several tenths of models and not
all simulations scenarios require all assertions enabled all the
time, therefore I'd like to come up with some technique to be
able to enable/disable a set of assertions as needed.

First it came to my mind to use 'define' to enable/disable each
individual assertion but I find it tedious and difficult to
maintain.

Anyone out there having an idea? Any pointers?


Hi Al,

Split your assertions over a number of vunits, or use the abort operator
to disable a set of assertions.
If you need more fine control you could parse the RTL file with a bit of
Tcl goodness and some regular expressions and uncomment/comment the
assertions as per the requirement.
There might be some disable/enable assertion control in your simulator
in which case you can script it up.

Good luck,
Hans
www.ht-lab.com

Quote:

Al

[1] this is cross-posted on comp.lang.verilog but the news editor
I'm currently using doesn't allow for setting the follow-up
field!


----Android NewsGroup Reader----
http://usenet.sinaapp.com/


elektroda.net NewsGroups Forum Index - VHDL Language - Disable/enable PSL assertions

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