Thu Jan 01, 1970 2:00 am
I'm about to start some work with assertions on our Verilog-AMS
models. Unfortunately we have several tenths of models and not
all simulations scenarios require all assertions enabled all the
time, therefore I'd like to come up with some technique to be
able to enable/disable a set of assertions as needed.
First it came to my mind to use 'define' to enable/disable each
individual assertion but I find it tedious and difficult to
Anyone out there having an idea? Any pointers?
----Android NewsGroup Reader----
Tue Oct 24, 2017 11:18 am
Look at the $assertoff() system task.
You can add as required in your testcase(s)