DEBUG a FIFO output on Virtex5 using CHIPESCOPE

Tue Jan 03, 2012 4:22 am   

Hi All,
I'm a relatively newbe of FPGA development.
We are working on a design involving BFSK modulator / demodulator pair.
We are usign the built-in FIFO18 component of Xilinx for Virtex5.
For some reason the fifo output seems to be NOT proper.
Could any of you suggest a way to investigate this, maybe using chipscope?
I tried to connect the Data output of the fiso to an ILA driven by rea
clock but the clock is much faster than the read enable signal so I see
lot of samples of the same value.
Any adie about hot to do?

Thanks a lot in advance

Best regards

Fabio Giovagnini
Aurion s.r.l.
Bologna (Italy)




---------------------------------------
Posted through http://www.FPGARelated.com

Tue Jan 03, 2012 2:30 pm   

fanakin wrote:

ChipScope has a feature that allows you to collect data only on cycles
that match a certain condition. This conditional storage uses the
same trigger logic as the normal trigger, so it is convenient to
define multiple triggers when you generate the ILA core. You can
use the read enable of the FIFO as a condition for storage. If
you also want to see surrounding cycles, you may need to add logic
to generate the storage condition you want, and just make sure to
place a KEEP attribute on the signal so it is available to ChipScope.

-- Gabor