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dc_shell and synthesis using existing gates

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Justin Undies
Guest

Tue Jul 06, 2004 8:20 pm   



Hi

I have a synthesised netlist obtained from Design Compiler. I want to
now make an "incremental" change to this netlist by modifying some
logic cone.

I have an RTL of the change that is to be made and would like to
synthesize this using only "spare" (unused) gate instances of the
original synthesized netlist.

Is it possible to use dc_shell to accomplish this synthesis ( -
synthesis using already existing gate instances only ? ) Has anybody
tried this with dc_shell before ? What are the
commands/constraints/attributes needed by dc_shell ?

Thanks much !

Justin

ka
Guest

Wed Jul 07, 2004 2:20 am   



On 6 Jul 2004 12:20:31 -0700, ssalem1_at_pacbell.net (Justin Undies)
wrote:

Quote:
Hi

I have a synthesised netlist obtained from Design Compiler. I want to
now make an "incremental" change to this netlist by modifying some
logic cone.

I have an RTL of the change that is to be made and would like to
synthesize this using only "spare" (unused) gate instances of the
original synthesized netlist.

Is it possible to use dc_shell to accomplish this synthesis ( -
synthesis using already existing gate instances only ? ) Has anybody
tried this with dc_shell before ? What are the
commands/constraints/attributes needed by dc_shell ?

Thanks much !

Justin

do a google on "eco compiler" and read the first hit. what you want is
not trivial. you may have to do it yourself manually or pay someone to
do it.
the way i have done it in the past was to implement the rtl changes
manually and find the gates either from the existing implementation or
use the spare gates. of course you have to make sure that the manual
implementation of the rtl changes are equivalent to the rtl by running
some formal verification tool on the final rtl vs final gate.

elektroda.net NewsGroups Forum Index - Synthesis - dc_shell and synthesis using existing gates

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