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Giuseppe Marullo
Guest
Mon Dec 12, 2011 10:32 am
Sorry for the naive question, but how do I capture a schematic with a D
and J-K FF that do have negated Q? I tried to draw the schematic with
WebISE 13.3 and there is not such a thing readily available.
TIA.
Giuseppe Marullo
RCIngham
Guest
Mon Dec 12, 2011 12:45 pm
You might be more likely to get an answer if you post this question at th
Xilinx forums, for example:
http://forums.xilinx.com/t5/Design-Entry/bd-p/DEENBD
---------------------------------------
Posted through
http://www.FPGARelated.com
Andy
Guest
Mon Dec 12, 2011 4:51 pm
On Dec 12, 3:32 am, Giuseppe Marullo
<giuseppe.marullonos...@iname.com> wrote:
Quote:
Sorry for the naive question, but how do I capture a schematic with a D
and J-K FF that do have negated Q? I tried to draw the schematic with
WebISE 13.3 and there is not such a thing readily available.
TIA.
Giuseppe Marullo
Use an inverter on the clock net. It will get absorbed into the FFs.
Andy
Michael Laajanen
Guest
Mon Dec 12, 2011 6:08 pm
Hi,
Giuseppe Marullo skrev 2011-12-12 10:32:
Quote:
Sorry for the naive question, but how do I capture a schematic with a D
and J-K FF that do have negated Q? I tried to draw the schematic with
WebISE 13.3 and there is not such a thing readily available.
TIA.
Giuseppe Marullo
When you run P&R the optimizing will reduce your design whenever
possible. Check the output of the build process and see what it says.
Or make a very tiny design then you can see in fpga_editor what the P&R
did do.
/michael
Ed McGettigan
Guest
Mon Dec 12, 2011 10:22 pm
On Dec 12, 6:51 am, Andy <jonesa...@comcast.net> wrote:
Quote:
On Dec 12, 3:32 am, Giuseppe Marullo
giuseppe.marullonos...@iname.com> wrote:
Sorry for the naive question, but how do I capture a schematic with a D
and J-K FF that do have negated Q? I tried to draw the schematic with
WebISE 13.3 and there is not such a thing readily available.
TIA.
Giuseppe Marullo
Use an inverter on the clock net. It will get absorbed into the FFs.
Andy
The OP asked for a "negated Q", which I would interpert as being an
invertor on the Q output and not on the CLK input.
Ed McGettigan
--
Xilinx Inc.
glen herrmannsfeldt
Guest
Mon Dec 12, 2011 10:34 pm
Ed McGettigan <ed.mcgettigan_at_xilinx.com> wrote:
(snip, someone wrote)
Quote:
Use an inverter on the clock net. It will get absorbed into the FFs.
The OP asked for a "negated Q", which I would interpert as being an
invertor on the Q output and not on the CLK input.
In any case, the inverter should be absorbed where possible,
and included elsewhere.
In the TTL days, it was usual for FF's to have Q and Qbar outputs,
with no extra inverter delay in the Qbar case.
But even more, the OP didn't ask about the logic, but how to
draw it. (Even though I don't especially like schematic capture.)
I suppose the schematic capture tools could add a Qbar output and
generate an inverter. Maybe they allow for inverting outputs by
adding circles. It is a tools question, not a logic question.
-- glen
Giuseppe Marullo
Guest
Mon Dec 12, 2011 11:31 pm
Quote:
adding circles. It is a tools question, not a logic question.
-- glen
Glen, exactly. I need to do the capture thing because it is not so
trivial to convert the schematic into verilog at first glance, and the
FF uses both Q and Qbar. I was thinking it was a fault from my
understanding of the tool, but qbar are missing on all FF i found in the
tool.
The other way would it be to write a custom block where inside a verilog
would implement the desired FF but maybe there is a simpler way.
Giuseppe Marullo
Giuseppe Marullo
Guest
Mon Dec 12, 2011 11:58 pm
On 12/12/2011 12:45 PM, RCIngham wrote:
Quote:
Jon Elson
Guest
Tue Dec 13, 2011 12:40 am
On 12/12/2011 04:31 PM, Giuseppe Marullo wrote:
Quote:
adding circles. It is a tools question, not a logic question.
-- glen
Glen, exactly. I need to do the capture thing because it is not so
trivial to convert the schematic into verilog at first glance, and the
FF uses both Q and Qbar. I was thinking it was a fault from my
understanding of the tool, but qbar are missing on all FF i found in the
tool.
The other way would it be to write a custom block where inside a verilog
would implement the desired FF but maybe there is a simpler way.
Giuseppe Marullo
If you are going to be using schematic entry, then it is quite easy to
build all the primitives you need out of simpler primitives and make
a custom library of them. I still do this on some CPLD interface
projects where simple definitions in schematic form are more concise.
I build N-way tristate buffers and tristate FFs and such that way.
Jon
glen herrmannsfeldt
Guest
Tue Dec 13, 2011 2:02 am
Giuseppe Marullo <giuseppe.marullonospam_at_iname.com> wrote:
Quote:
adding circles. It is a tools question, not a logic question.
Glen, exactly. I need to do the capture thing because it is not so
trivial to convert the schematic into verilog at first glance, and the
FF uses both Q and Qbar.
Personally, I think I can write verilog faster than I can get
the lines drawn for schematic capture, but others may be different.
Quote:
I was thinking it was a fault from my understanding of the tool,
but qbar are missing on all FF i found in the tool.
For FPGAs, inverters will usually be moved into the logic before
or after, changing bits in the appropriate LUT. So no delay difference.
That wasn't true in TTL. So, now the reason for them is gone,
and the tools don't support them.
Quote:
The other way would it be to write a custom block where inside a verilog
would implement the desired FF but maybe there is a simpler way.
On some, you can draw your own symbol, including the circles.
-- glen
Ed McGettigan
Guest
Tue Dec 13, 2011 5:15 am
On Dec 12, 2:31 pm, Giuseppe Marullo
<giuseppe.marullonos...@iname.com> wrote:
Quote:
adding circles. It is a tools question, not a logic question.
-- glen
Glen, exactly. I need to do the capture thing because it is not so
trivial to convert the schematic into verilog at first glance, and the
FF uses both Q and Qbar. I was thinking it was a fault from my
understanding of the tool, but qbar are missing on all FF i found in the
tool.
The other way would it be to write a custom block where inside a verilog
would implement the desired FF but maybe there is a simpler way.
Giuseppe Marullo
If it can be drawn in a schematic in can be written in Verilog and
probably written faster than it can be drawn.
always @ (posedge clk)
begin
q <= d
end
assign qbar = !q;
There isn't anything unique about a Q or Qbar. These existed at one
point in discrete logic when it was far more difficult to add an
discrete inverter on a PCB and have the inverted output was very
beneficial, but in an FPGA or ASIC it just doesn't matter anymore. If
you need Qbar then just take Q and invert it (Qbar=!Q) and then apply
it to the next functional bit. In an FPGA the inversion will be
absorbed into the next LUT function or the D, CE or RST pin of the
register that it feeds.
Note: If the Q is feeding an output buffer (OBUF) then you will need
to invert the signal going into the D of the F/F instead in order to
pack the register into the IOB.
Ed McGettigan
--
Xilinx Inc.
Gabor
Guest
Tue Dec 13, 2011 2:54 pm
Ed McGettigan wrote:
Quote:
On Dec 12, 2:31 pm, Giuseppe Marullo
giuseppe.marullonos...@iname.com> wrote:
adding circles. It is a tools question, not a logic question.
-- glen
Glen, exactly. I need to do the capture thing because it is not so
trivial to convert the schematic into verilog at first glance, and the
FF uses both Q and Qbar. I was thinking it was a fault from my
understanding of the tool, but qbar are missing on all FF i found in the
tool.
The other way would it be to write a custom block where inside a verilog
would implement the desired FF but maybe there is a simpler way.
Giuseppe Marullo
If it can be drawn in a schematic in can be written in Verilog and
probably written faster than it can be drawn.
always @ (posedge clk)
begin
q <= d
end
assign qbar = !q;
To be true to the original, you should have written:
always @ (posedge clk)
begin
q <= d;
qbar <= !d;
end
In the FPGA it wouldn't matter, because the inversion would
not create another delay. Also if you're actually copying
a schematic that was implemented in TTL, there could be other
issues if the original did not use a fully synchronous design
technique.
Quote:
There isn't anything unique about a Q or Qbar. These existed at one
point in discrete logic when it was far more difficult to add an
discrete inverter on a PCB and have the inverted output was very
beneficial, but in an FPGA or ASIC it just doesn't matter anymore. If
you need Qbar then just take Q and invert it (Qbar=!Q) and then apply
it to the next functional bit. In an FPGA the inversion will be
absorbed into the next LUT function or the D, CE or RST pin of the
register that it feeds.
Note: If the Q is feeding an output buffer (OBUF) then you will need
to invert the signal going into the D of the F/F instead in order to
pack the register into the IOB.
Ed McGettigan
--
Xilinx Inc.
Note that placing the inverter before or after the flip-flop
can make a difference if it actually means adding a LUT to
do the inversion, and also note that given the freedom the
synthesis tools can move the LUT before or after the flip-flop
to help meet timing (register balancing enabled). So regardless
of how you enter the code, the result after synthesis and map
can vary. Don't think that just because you're entering schematics
that the actual implementation will match your schematic. At
least for FPGA's, ISE treats schematic entry just like structural
HDL and will do all of the same optimizations. From ISE you
should also have the option to view the "technology schematic"
after translation to see what became of your "inverter".
I personally like schematic entry but detest Xilinx's implementation
of it, so I haven't used it since they dropped the Aldec front-end
tools after Foundation 4.1i. In those days if I didn't see the
symbol I needed, I'd write Abel code and create a symbol from it.
With the newer ISE, you can also use Verilog of VHDL to enter
blocks, and then create a schematic symbol from the HDL. Or
as suggested you can create hierarchical symbols with the
schematic editor. There are many ways to skin a cat...
-- Gabor
Ed McGettigan
Guest
Tue Dec 13, 2011 6:22 pm
On Dec 13, 5:54 am, Gabor <ga...@szakacs.invalid> wrote:
Quote:
Ed McGettigan wrote:
On Dec 12, 2:31 pm, Giuseppe Marullo
giuseppe.marullonos...@iname.com> wrote:
adding circles. It is a tools question, not a logic question.
-- glen
Glen, exactly. I need to do the capture thing because it is not so
trivial to convert the schematic into verilog at first glance, and the
FF uses both Q and Qbar. I was thinking it was a fault from my
understanding of the tool, but qbar are missing on all FF i found in the
tool.
The other way would it be to write a custom block where inside a verilog
would implement the desired FF but maybe there is a simpler way.
Giuseppe Marullo
If it can be drawn in a schematic in can be written in Verilog and
probably written faster than it can be drawn.
always @ (posedge clk)
begin
q <= d
end
assign qbar = !q;
To be true to the original, you should have written:
always @ (posedge clk)
begin
q <= d;
qbar <= !d;
end
In the FPGA it wouldn't matter, because the inversion would
not create another delay. Also if you're actually copying
a schematic that was implemented in TTL, there could be other
issues if the original did not use a fully synchronous design
technique.
There isn't anything unique about a Q or Qbar. These existed at one
point in discrete logic when it was far more difficult to add an
discrete inverter on a PCB and have the inverted output was very
beneficial, but in an FPGA or ASIC it just doesn't matter anymore. If
you need Qbar then just take Q and invert it (Qbar=!Q) and then apply
it to the next functional bit. In an FPGA the inversion will be
absorbed into the next LUT function or the D, CE or RST pin of the
register that it feeds.
Note: If the Q is feeding an output buffer (OBUF) then you will need
to invert the signal going into the D of the F/F instead in order to
pack the register into the IOB.
Ed McGettigan
--
Xilinx Inc.
Note that placing the inverter before or after the flip-flop
can make a difference if it actually means adding a LUT to
do the inversion, and also note that given the freedom the
synthesis tools can move the LUT before or after the flip-flop
to help meet timing (register balancing enabled). So regardless
of how you enter the code, the result after synthesis and map
can vary. Don't think that just because you're entering schematics
that the actual implementation will match your schematic. At
least for FPGA's, ISE treats schematic entry just like structural
HDL and will do all of the same optimizations. From ISE you
should also have the option to view the "technology schematic"
after translation to see what became of your "inverter".
I personally like schematic entry but detest Xilinx's implementation
of it, so I haven't used it since they dropped the Aldec front-end
tools after Foundation 4.1i. In those days if I didn't see the
symbol I needed, I'd write Abel code and create a symbol from it.
With the newer ISE, you can also use Verilog of VHDL to enter
blocks, and then create a schematic symbol from the HDL. Or
as suggested you can create hierarchical symbols with the
schematic editor. There are many ways to skin a cat...
-- Gabor- Hide quoted text -
- Show quoted text -- Hide quoted text -
- Show quoted text -
Gabor,
Your code would generate two registers one for q and one for qbar.
IMHO, this is further removed from the original intent and would use
more resource than an inversion that would likely be merged into the
next LUT or register input.
Ed McGettigan
--
Xilinx Inc.
rickman
Guest
Tue Dec 13, 2011 7:56 pm
On Dec 13, 11:22 am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:
Quote:
On Dec 13, 5:54 am, Gabor <ga...@szakacs.invalid> wrote:
Ed McGettigan wrote:
On Dec 12, 2:31 pm, Giuseppe Marullo
giuseppe.marullonos...@iname.com> wrote:
adding circles. It is a tools question, not a logic question.
-- glen
Glen, exactly. I need to do the capture thing because it is not so
trivial to convert the schematic into verilog at first glance, and the
FF uses both Q and Qbar. I was thinking it was a fault from my
understanding of the tool, but qbar are missing on all FF i found in the
tool.
The other way would it be to write a custom block where inside a verilog
would implement the desired FF but maybe there is a simpler way.
Giuseppe Marullo
If it can be drawn in a schematic in can be written in Verilog and
probably written faster than it can be drawn.
always @ (posedge clk)
begin
q <= d
end
assign qbar = !q;
To be true to the original, you should have written:
always @ (posedge clk)
begin
q <= d;
qbar <= !d;
end
In the FPGA it wouldn't matter, because the inversion would
not create another delay. Also if you're actually copying
a schematic that was implemented in TTL, there could be other
issues if the original did not use a fully synchronous design
technique.
There isn't anything unique about a Q or Qbar. These existed at one
point in discrete logic when it was far more difficult to add an
discrete inverter on a PCB and have the inverted output was very
beneficial, but in an FPGA or ASIC it just doesn't matter anymore. If
you need Qbar then just take Q and invert it (Qbar=!Q) and then apply
it to the next functional bit. In an FPGA the inversion will be
absorbed into the next LUT function or the D, CE or RST pin of the
register that it feeds.
Note: If the Q is feeding an output buffer (OBUF) then you will need
to invert the signal going into the D of the F/F instead in order to
pack the register into the IOB.
Ed McGettigan
--
Xilinx Inc.
Note that placing the inverter before or after the flip-flop
can make a difference if it actually means adding a LUT to
do the inversion, and also note that given the freedom the
synthesis tools can move the LUT before or after the flip-flop
to help meet timing (register balancing enabled). So regardless
of how you enter the code, the result after synthesis and map
can vary. Don't think that just because you're entering schematics
that the actual implementation will match your schematic. At
least for FPGA's, ISE treats schematic entry just like structural
HDL and will do all of the same optimizations. From ISE you
should also have the option to view the "technology schematic"
after translation to see what became of your "inverter".
I personally like schematic entry but detest Xilinx's implementation
of it, so I haven't used it since they dropped the Aldec front-end
tools after Foundation 4.1i. In those days if I didn't see the
symbol I needed, I'd write Abel code and create a symbol from it.
With the newer ISE, you can also use Verilog of VHDL to enter
blocks, and then create a schematic symbol from the HDL. Or
as suggested you can create hierarchical symbols with the
schematic editor. There are many ways to skin a cat...
-- Gabor- Hide quoted text -
- Show quoted text -- Hide quoted text -
- Show quoted text -
Gabor,
Your code would generate two registers one for q and one for qbar.
IMHO, this is further removed from the original intent and would use
more resource than an inversion that would likely be merged into the
next LUT or register input.
Ed McGettigan
--
Xilinx Inc.
I'm pretty sure most tools are smart enough to understand that the one
description is equivalent to the other and optimize the code to a
single register and shove the inversion into the following logic,
assuming there is any. Am I wrong about this?
I know I have seen equivalent registers combined into one when I was
trying to reduce the fan out on a net.
Rick
glen herrmannsfeldt
Guest
Tue Dec 13, 2011 8:57 pm
Ed McGettigan <ed.mcgettigan_at_xilinx.com> wrote:
Quote:
On Dec 13, 5:54 am, Gabor <ga...@szakacs.invalid> wrote:
(snip)
Quote:
To be true to the original, you should have written:
always @ (posedge clk)
begin
q <= d;
qbar <= !d;
end
In the FPGA it wouldn't matter, because the inversion would
not create another delay. Also if you're actually copying
a schematic that was implemented in TTL, there could be other
issues if the original did not use a fully synchronous design
technique.
always @(posedge clk)
begin
q = #1 d;
qbar = #1 !d;
end
(snip)
Quote:
Note that placing the inverter before or after the flip-flop
can make a difference if it actually means adding a LUT to
do the inversion, and also note that given the freedom the
synthesis tools can move the LUT before or after the flip-flop
to help meet timing (register balancing enabled).
Your code would generate two registers one for q and one for qbar.
IMHO, this is further removed from the original intent and would use
more resource than an inversion that would likely be merged into the
next LUT or register input.
The tools are very good at removing duplicate register. Even from
different modules at different nesting levels, they will still be
removed, such that only one is used. (There is a message when it
does it.)
It might even be that a single register can be duplicated to help
meet the timing requirements, though I don't remember seeing it
do that.
-- glen
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