D-Type Flip flop with negated Q in Webise for a schematic ca

On Dec 13, 11:22 am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:





On Dec 13, 5:54 am, Gabor <ga...@szakacs.invalid> wrote:

Ed McGettigan wrote:
On Dec 12, 2:31 pm, Giuseppe Marullo
giuseppe.marullonos...@iname.com> wrote:
adding circles.  It is a tools question, not a logic question.
-- glen
Glen, exactly. I need to do the capture thing because it is not so
trivial to convert the schematic into verilog at first glance, and the
FF uses both Q and Qbar. I was thinking it was a fault from my
understanding of the tool, but qbar are missing on all FF i found in the
tool.

The other way would it be to write a custom block where inside a verilog
would implement the desired FF but maybe there is a simpler way.

Giuseppe Marullo

If it can be drawn in a schematic in can be written in Verilog and
probably written faster than it can be drawn.

always @ (posedge clk)
begin
   q <= d
end

assign qbar = !q;

To be true to the original, you should have written:

always @ (posedge clk)
begin
   q <= d;
   qbar <= !d;
end

In the FPGA it wouldn't matter, because the inversion would
not create another delay.  Also if you're actually copying
a schematic that was implemented in TTL, there could be other
issues if the original did not use a fully synchronous design
technique.

There isn't anything unique about a Q or Qbar.  These existed at one
point in discrete logic when it was far more difficult to add an
discrete inverter on a PCB and have the inverted output was very
beneficial, but in an FPGA or ASIC it just doesn't matter anymore.  If
you need Qbar then just take Q and invert it (Qbar=!Q) and then apply
it to the next functional bit.  In an FPGA the inversion will be
absorbed into the next LUT function or the D, CE or RST pin of the
register that it feeds.

Note: If the Q is feeding an output buffer (OBUF) then you will need
to invert the signal going into the D of the F/F instead in order to
pack the register into the IOB.

Ed McGettigan
--
Xilinx Inc.

Note that placing the inverter before or after the flip-flop
can make a difference if it actually means adding a LUT to
do the inversion, and also note that given the freedom the
synthesis tools can move the LUT before or after the flip-flop
to help meet timing (register balancing enabled).  So regardless
of how you enter the code, the result after synthesis and map
can vary.  Don't think that just because you're entering schematics
that the actual implementation will match your schematic.  At
least for FPGA's, ISE treats schematic entry just like structural
HDL and will do all of the same optimizations.  From ISE you
should also have the option to view the "technology schematic"
after translation to see what became of your "inverter".

I personally like schematic entry but detest Xilinx's implementation
of it, so I haven't used it since they dropped the Aldec front-end
tools after Foundation 4.1i.  In those days if I didn't see the
symbol I needed, I'd write Abel code and create a symbol from it.
With the newer ISE, you can also use Verilog of VHDL to enter
blocks, and then create a schematic symbol from the HDL.  Or
as suggested you can create hierarchical symbols with the
schematic editor.  There are many ways to skin a cat...

-- Gabor- Hide quoted text -

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Gabor,

Your code would generate two registers one for q and one for qbar.
IMHO, this is further removed from the original intent and would use
more resource than an inversion that would likely be merged into the
next LUT or register input.

Ed McGettigan
--
Xilinx Inc.

I'm pretty sure most tools are smart enough to understand that the one
description is equivalent to the other and optimize the code to a
single register and shove the inversion into the following logic,
assuming there is any.  Am I wrong about this?

I know I have seen equivalent registers combined into one when I was
trying to reduce the fan out on a net.

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