EDAboard.com | EDAboard.eu | EDAboard.de | EDAboard.co.uk | RTV forum PL | NewsGroups PL

Cyclone III SFL Megafunction

elektroda.net NewsGroups Forum Index - VHDL Language - Cyclone III SFL Megafunction

Steffen Koepf
Guest

Wed Jan 20, 2010 12:27 am   



Hello,

one more question Wink
i want to reprogram the configuration from a ATMega with
it's ISP interface. Therefore i created a megafunction and
routed the controlling signals out of the FPGA to the
ATMega SPI Interface. Now there are nasty warnings from
the fitter that i want to get rid of.

Warning: Ignored reserve pin assignment to SPI programming pin Data[1]/ASDO
Warning: Ignored reserve pin assignment to SPI programming pin FLASH_nCE/nCSO
Warning: Ignored reserve pin assignment to SPI programming pin DCLK
Warning: Ignored reserve pin assignment to SPI programming pin Data[0]

Is a reserve pin assignment the default assignment of all pins not
directly assigned a value? What to do here?

Next:

Warning: Some pins have incomplete I/O assignments. Refer to the I/O Assignment
Warnings report for details

In the I/O Assignment Warnings it complains that the driving strength is
not specified of megafunction internal signals like
sfl:U16|altserial_flash_loader:altserial_flash_loader_component|\GEN_ASMI_TYPE_1:asmi_inst~ALTERA_DATA0
But copying this signal in the assignment editor and assigning a current
drive strength seems to have no effect.

Thanks in advance,

Steffen

Charles Steinkuehler
Guest

Tue Feb 02, 2010 5:50 am   



On 1/19/2010 4:27 PM, Steffen Koepf wrote:
Quote:
Hello,

one more question Wink
i want to reprogram the configuration from a ATMega with
it's ISP interface. Therefore i created a megafunction and
routed the controlling signals out of the FPGA to the
ATMega SPI Interface. Now there are nasty warnings from
the fitter that i want to get rid of.

Warning: Ignored reserve pin assignment to SPI programming pin Data[1]/ASDO
Warning: Ignored reserve pin assignment to SPI programming pin FLASH_nCE/nCSO
Warning: Ignored reserve pin assignment to SPI programming pin DCLK
Warning: Ignored reserve pin assignment to SPI programming pin Data[0]

Is a reserve pin assignment the default assignment of all pins not
directly assigned a value? What to do here?

You need to allow these pins to be used as general-purpose I/O. By
default, Quartus reserves these pins and does not let you assign signals
to them. Go to:

Assignments -> Settings -> Device -> Device and Pin Options ->
Dual-Purpose Pins

....select the pins you need to assign signals to, and change their
setting to "Use as regular I/O"

--
Charles Steinkuehler
charles_at_steinkuehler.net

Charles Steinkuehler
Guest

Tue Feb 02, 2010 5:55 am   



On 1/19/2010 4:27 PM, Steffen Koepf wrote:
Quote:
Hello,

one more question Wink
i want to reprogram the configuration from a ATMega with
it's ISP interface. Therefore i created a megafunction and
routed the controlling signals out of the FPGA to the
ATMega SPI Interface. Now there are nasty warnings from
the fitter that i want to get rid of.

Warning: Ignored reserve pin assignment to SPI programming pin Data[1]/ASDO
Warning: Ignored reserve pin assignment to SPI programming pin FLASH_nCE/nCSO
Warning: Ignored reserve pin assignment to SPI programming pin DCLK
Warning: Ignored reserve pin assignment to SPI programming pin Data[0]

Is a reserve pin assignment the default assignment of all pins not
directly assigned a value? What to do here?

You need to allow these pins to be used as general-purpose I/O. By
default, Quartus reserves these pins and does not let you assign signals
to them. Go to:

Assignments -> Settings -> Device -> Device and Pin Options ->
Dual-Purpose Pins

....select the pins you need to assign signals to, and change their
setting to "Use as regular I/O"

--
Charles Steinkuehler
charles_at_steinkuehler.net

Charles Steinkuehler
Guest

Tue Feb 02, 2010 6:57 am   



On Jan 19, 4:27 pm, Steffen Koepf <Taxman-use...@opaya.de> wrote:
Quote:
Hello,

one more question Wink
i want to reprogram the configuration from a ATMega with
it's ISP interface. Therefore i created a megafunction and
routed the controlling signals out of the FPGA to the
ATMega SPI Interface. Now there are nasty warnings from
the fitter that i want to get rid of.

Warning: Ignored reserve pin assignment to SPI programming pin Data[1]/ASDO
Warning: Ignored reserve pin assignment to SPI programming pin FLASH_nCE/nCSO
Warning: Ignored reserve pin assignment to SPI programming pin DCLK
Warning: Ignored reserve pin assignment to SPI programming pin Data[0]

Is a reserve pin assignment the default assignment of all pins not
directly assigned a value? What to do here?

You need to allow these pins to be used as general-purpose I/O. By
default, Quartus reserves these pins and does not let you assign
signals to them. Go to:

Assignments -> Settings -> Device -> Device and Pin Options ->
Dual-Purpose Pins

....select the pins you need to assign signals to, and change their
setting to "Use as regular I/O"

--
Charles Steinkuehler
charles_at_steinkuehler.net

elektroda.net NewsGroups Forum Index - VHDL Language - Cyclone III SFL Megafunction

Arabic versionBulgarian versionCatalan versionCzech versionDanish versionGerman versionGreek versionEnglish versionSpanish versionFinnish versionFrench versionHindi versionCroatian versionIndonesian versionItalian versionHebrew versionJapanese versionKorean versionLithuanian versionLatvian versionDutch versionNorwegian versionPolish versionPortuguese versionRomanian versionRussian versionSlovak versionSlovenian versionSerbian versionSwedish versionTagalog versionUkrainian versionVietnamese versionChinese version
RTV map EDAboard.com map News map EDAboard.eu map EDAboard.de map EDAboard.co.uk map Opony