EDAboard.com | EDAboard.de | EDAboard.co.uk | WTWH Media

Creating virtual channel for router using verilog

Ask a question - edaboard.com

elektroda.net NewsGroups Forum Index - VHDL Language - Creating virtual channel for router using verilog

ash7724
Guest

Mon Apr 04, 2016 7:30 am   



I wanted to design virtual channels for FIFO. I have one main FIFO whose data is to be sent to any one of the three virtual channels. Each virtual channel has a FIFO.
Plz help me in designing this,

rickman
Guest

Tue Apr 05, 2016 7:30 am   



On 4/4/2016 2:11 AM, ash7724 wrote:
Quote:
I wanted to design virtual channels for FIFO. I have one main FIFO whose data is to be sent to any one of the three virtual channels. Each virtual channel has a FIFO.
Plz help me in designing this,


Ok, how do you distinguish the three channels?

--

Rick

elektroda.net NewsGroups Forum Index - VHDL Language - Creating virtual channel for router using verilog

Ask a question - edaboard.com

Arabic version Bulgarian version Catalan version Czech version Danish version German version Greek version English version Spanish version Finnish version French version Hindi version Croatian version Indonesian version Italian version Hebrew version Japanese version Korean version Lithuanian version Latvian version Dutch version Norwegian version Polish version Portuguese version Romanian version Russian version Slovak version Slovenian version Serbian version Swedish version Tagalog version Ukrainian version Vietnamese version Chinese version Turkish version
EDAboard.com map