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aadi
Guest

Fri Oct 16, 2015 3:36 pm   



i have learned every aspect of VHDL but i still can't exersise it to make complex program.
i need a code for data encryption standard and also for key generation. but i can't get a single way to do so
plzz help me

KJ
Guest

Fri Oct 16, 2015 3:36 pm   



On Friday, October 16, 2015 at 5:36:53 AM UTC-4, aadi wrote:
Quote:
i have learned every aspect of VHDL but i still can't exersise it to make complex program.
i need a code for data encryption standard and also for key generation. but i can't get a single way to do so
plzz help me


Stating what you say you 'need' and not showing what you've 'done' doesn't typically motivate anybody to help.

Some suggestions:
- Post some code for people to review and comment
- Pay somebody to write the code for you
- English may not be your first language, but 'plzz' is not even close to 'please'...it's closer to 'pizza'. Showing some bit of professionalism is often useful

Kevin

Thomas Stanka
Guest

Fri Oct 16, 2015 3:36 pm   



Am Freitag, 16. Oktober 2015 11:36:53 UTC+2 schrieb aadi:
Quote:
i have learned every aspect of VHDL but i still can't exersise it to make complex program.
i need a code for data encryption standard and also for key generation. but i can't get a single way to do so
plzz help me


In general, it is agreed that writing a "Program" requires you to have Software and Compiler that generates a Program out of your Software.

VHDL is mainly a hardware description language, I know no Compiler allowing you to generate a executeable out of VHDL, instead you will find several Simulators, that allow you to simulate the Code you wrote.

If you have learned every aspect of VHDL this is nothing new for you, so your problem should be with the data encryption, not with HDL descripton itself, so you might ask in a group dealing with encyption standard.

A VHDL code for DES can easily take some man-month work force. If you need easy way register by open cores and download the DES core from there.

In this group you should provide specific questions in order to receive specific answers.

regards Thomas

glen herrmannsfeldt
Guest

Sat Oct 17, 2015 2:27 am   



aadi <aanchalgurawa_at_gmail.com> wrote:
Quote:
i have learned every aspect of VHDL but i still can't exersise it
to make complex program.


I started VHDL, and though I have never written a 'program' in it, I
have designed some fairly complicated logic that actually works.

I won't claim to undestand even half of VHDL, as they are adding to it
faster than I can learn, and faster than the systems I use it with
can keep up.

(I had some years of verilog before, but only learned a small fraction
of VHDL before I knew enough to start writing it.)

Quote:
i need a code for data encryption standard and also for key generation.
but i can't get a single way to do so


Do remember that VHDL is not a software programming language.

-- glen


Guest

Tue Oct 20, 2015 8:34 am   



On Friday, October 16, 2015 at 12:36:53 PM UTC+3, aadi wrote:
Quote:
i have learned every aspect of VHDL but i still can't exersise it to make complex program.
i need a code for data encryption standard and also for key generation. but i can't get a single way to do so
plzz help me


You may want to see some examples. A simple UART project
http://bknpk.ddns.net/my_web/MiscellaneousHW/UART/uart_tx_1.html
A more complex design based on some free open IP stack. It also synthesized with Xilinx free XST and simulated with post NGD net-list.
All is done with the free VHDL simulator GHDL
http://bknpk.ddns.net/my_web/IP_STACK/start_1.html

aadi
Guest

Fri Oct 23, 2015 1:48 pm   



Thanks Kevin for your comment.
Well here is my code its running only for one round but my mentor told me to change it into a behavioural code and not to use for loop.


key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1);
key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1);
end if;
when 10 =>
if (decipher = '1') then
key_l(0 to 27) <= key_l(26 to 27) & key_l(0 to 25);
key_r(0 to 27) <= key_r(26 to 27) & key_r(0 to 25);
else
key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1);
key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1);
end if;
when 11 =>
if (decipher = '1') then
key_l(0 to 27) <= key_l(26 to 27) & key_l(0 to 25);
key_r(0 to 27) <= key_r(26 to 27) & key_r(0 to 25);
else
key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1);
key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1);
end if;
when 12 =>
if (decipher = '1') then
key_l(0 to 27) <= key_l(26 to 27) & key_l(0 to 25);
key_r(0 to 27) <= key_r(26 to 27) & key_r(0 to 25);
else
key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1);
key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1);
end if;
when 13 =>
if (decipher = '1') then
key_l(0 to 27) <= key_l(26 to 27) & key_l(0 to 25);
key_r(0 to 27) <= key_r(26 to 27) & key_r(0 to 25);
else
key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1);
key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1);
end if;
when 14 =>
if (decipher = '1') then
key_l(0 to 27) <= key_l(26 to 27) & key_l(0 to 25);
key_r(0 to 27) <= key_r(26 to 27) & key_r(0 to 25);
else
key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1);
key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1);
end if;
when 15 =>
if (decipher = '1') then
key_l(0 to 27) <= key_l(27) & key_l(0 to 26);
key_r(0 to 27) <= key_r(27) & key_r(0 to 26);
else
key_l(0 to 27) <= key_l(1 to 27) & key_l(0);
key_r(0 to 27) <= key_r(1 to 27) & key_r(0);
end if;
when others =>
end case;
end if;

end process Key;

cntrl: process (clk, dirtn)
variable count : integer range 0 to 15:=0;
begin

if (rising_edge(clk) and clk='1') then
if decipher = '0' then
if (dirtn='1') then
count:= count+ 1;
counter<=count;
else
if decipher = '1' then
count:= count- 1;
counter<=count;
end if;
end if;
end if;
end if;
end process cntrl;
end behavioural;

Igmar Palsenberg
Guest

Wed Oct 28, 2015 2:06 pm   



Op vrijdag 16 oktober 2015 11:36:53 UTC+2 schreef aadi:
> i have learned every aspect of VHDL but i still can't exersise it to make complex program.

It's VHDL, not C or Java. VHDL is a description, not a program.

> i need a code for data encryption standard and also for key generation. but i can't get a single way to do so

What is the question ? The're plenty of open sources VHDL examples available, lots of them on opencores.


Igmar

rickman
Guest

Wed Oct 28, 2015 10:29 pm   



On 10/28/2015 8:06 AM, Igmar Palsenberg wrote:
Quote:
Op vrijdag 16 oktober 2015 11:36:53 UTC+2 schreef aadi:
i have learned every aspect of VHDL but i still can't exersise it to make complex program.

It's VHDL, not C or Java. VHDL is a description, not a program.


That's not very fair. VHDL is used to describe hardware, but it is a
perfectly good programming language too. That is how we use it for test
benches.


Quote:
i need a code for data encryption standard and also for key generation. but i can't get a single way to do so

What is the question ? The're plenty of open sources VHDL examples available, lots of them on opencores.


Igmar



--

Rick

glen herrmannsfeldt
Guest

Thu Oct 29, 2015 12:39 am   



rickman <gnuarm_at_gmail.com> wrote:
> On 10/28/2015 8:06 AM, Igmar Palsenberg wrote:

(snip on VHDL and programs)

Quote:
It's VHDL, not C or Java. VHDL is a description, not a program.

That's not very fair. VHDL is used to describe hardware, but it is a
perfectly good programming language too. That is how we use it for test
benches.


I think I also don't like the use of the word 'program' even in
the case of test benches.

To me, program has too much implication of sequential execution
(even in the case of parallel programming) that I think some other
word should be used.

I might use design, which I think works in the case of hardware
and test benches, which both need to be designed, if not described.

Though test benches could also be described, even if they aren't
hardware.

(But the idea of a test bench comes from the days when they were
hardware, even furniture.)

-- glen

Igmar Palsenberg
Guest

Sat Oct 31, 2015 3:16 pm   



Op woensdag 28 oktober 2015 17:29:38 UTC+1 schreef rickman:
Quote:
On 10/28/2015 8:06 AM, Igmar Palsenberg wrote:
Op vrijdag 16 oktober 2015 11:36:53 UTC+2 schreef aadi:
i have learned every aspect of VHDL but i still can't exersise it to make complex program.

It's VHDL, not C or Java. VHDL is a description, not a program.

That's not very fair. VHDL is used to describe hardware, but it is a
perfectly good programming language too. That is how we use it for test
benches.


That's not it's primary goal. That the language allows it, sure, but that doesn't mean it's build for that. Doing C or VHDL requires a totally different mindset.


Igmar

rickman
Guest

Sun Nov 01, 2015 8:30 am   



On 10/28/2015 6:39 PM, glen herrmannsfeldt wrote:
Quote:
rickman <gnuarm_at_gmail.com> wrote:
On 10/28/2015 8:06 AM, Igmar Palsenberg wrote:

(snip on VHDL and programs)

It's VHDL, not C or Java. VHDL is a description, not a program.

That's not very fair. VHDL is used to describe hardware, but it is a
perfectly good programming language too. That is how we use it for test
benches.

I think I also don't like the use of the word 'program' even in
the case of test benches.

To me, program has too much implication of sequential execution
(even in the case of parallel programming) that I think some other
word should be used.

I might use design, which I think works in the case of hardware
and test benches, which both need to be designed, if not described.

Though test benches could also be described, even if they aren't
hardware.

(But the idea of a test bench comes from the days when they were
hardware, even furniture.)


I just call it "code".

--

Rick

rickman
Guest

Sun Nov 01, 2015 8:30 am   



On 10/31/2015 9:16 AM, Igmar Palsenberg wrote:
Quote:
Op woensdag 28 oktober 2015 17:29:38 UTC+1 schreef rickman:
On 10/28/2015 8:06 AM, Igmar Palsenberg wrote:
Op vrijdag 16 oktober 2015 11:36:53 UTC+2 schreef aadi:
i have learned every aspect of VHDL but i still can't exersise it to make complex program.

It's VHDL, not C or Java. VHDL is a description, not a program.

That's not very fair. VHDL is used to describe hardware, but it is a
perfectly good programming language too. That is how we use it for test
benches.

That's not it's primary goal. That the language allows it, sure, but that doesn't mean it's build for that. Doing C or VHDL requires a totally different mindset.


I think your distinction is pointless. You said "VHDL is a description,
not a program" and I have you an example when this is not true. End of
discussion for me.

As to the "mindset", there was a software designer who wanted to code an
FPGA in VHDL and came here asking for advice. We told him about how he
needed to adjust his thinking to design hardware and not code software.
I wrote to him personally to explain why this was important and came
close to getting some consulting time with his firm. In the end his
bosses had faith that he could do a good job and so he wrote the code
himself, without any trouble.

I learned that although I was a hardware person who was able to more
easily think about the hardware I was designing as gates and register,
this is *not* required, rather you *can* write VHDL as a sequential
language as long as you understand the various processes were all in
parallel. Parallel processes are not unique to hardware.

The really funny part was that the guy talked his bosses into sending me
a small check for the time I spent helping him while I insisted that was
just the cost of marketing for me and it was not needed. Not very often
I tell customers to *not* pay me. Lol

--

Rick

Andy
Guest

Mon Nov 02, 2015 10:58 pm   



Any coder worth his salt must know his/her compiler, be it C or VHDL. For HDLs, that typically means we need to know 2 different compilers (simulator and synthesis tools).

Even in purely sequential languages, the best compilers optimize the object code for the processor's inherent parallel execution capabilities based on dependencies, the same as a VHDL synthesis tool does for sequential code in processes and subprograms.

I agree that there are times (e.g. synchronization boundaries) where we need to code very close to the HW we need.

But at other times, coding for behavior (think throughput and clock cycles of latency) rather than HW (think gates and registers), solves more problems (will the HW behave the way we want?)

Otherwise, we leave 90% of the synthesis tool's capability on the table (we do its job for it by darn near coding a netlist).

Andy


Guest

Wed Nov 04, 2015 8:23 am   



Am Freitag, 23. Oktober 2015 09:48:40 UTC+2 schrieb aadi:
Quote:
Thanks Kevin for your comment.
Well here is my code its running only for one round but my mentor told me to change it into a behavioural code and not to use for loop.


key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1);
key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1);
end if;
when 10 =
if (decipher = '1') then
key_l(0 to 27) <= key_l(26 to 27) & key_l(0 to 25);
key_r(0 to 27) <= key_r(26 to 27) & key_r(0 to 25);
else
key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1);
key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1);
end if;
when 11 =
if (decipher = '1') then
key_l(0 to 27) <= key_l(26 to 27) & key_l(0 to 25);
key_r(0 to 27) <= key_r(26 to 27) & key_r(0 to 25);
else
key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1);
key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1);
end if;
when 12 =
if (decipher = '1') then
key_l(0 to 27) <= key_l(26 to 27) & key_l(0 to 25);
key_r(0 to 27) <= key_r(26 to 27) & key_r(0 to 25);
else
key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1);
key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1);
end if;
when 13 =
if (decipher = '1') then
key_l(0 to 27) <= key_l(26 to 27) & key_l(0 to 25);
key_r(0 to 27) <= key_r(26 to 27) & key_r(0 to 25);
else
key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1);
key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1);
end if;
when 14 =
if (decipher = '1') then
key_l(0 to 27) <= key_l(26 to 27) & key_l(0 to 25);
key_r(0 to 27) <= key_r(26 to 27) & key_r(0 to 25);
else
key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1);
key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1);
end if;
when 15 =
if (decipher = '1') then
key_l(0 to 27) <= key_l(27) & key_l(0 to 26);
key_r(0 to 27) <= key_r(27) & key_r(0 to 26);
else
key_l(0 to 27) <= key_l(1 to 27) & key_l(0);
key_r(0 to 27) <= key_r(1 to 27) & key_r(0);
end if;
when others =
end case;
end if;

end process Key;

cntrl: process (clk, dirtn)
variable count : integer range 0 to 15:=0;
begin

if (rising_edge(clk) and clk='1') then
if decipher = '0' then
if (dirtn='1') then
count:= count+ 1;
counter<=count;
else
if decipher = '1' then
count:= count- 1;
counter<=count;
end if;
end if;
end if;
end if;
end process cntrl;
end behavioural;


Hi,
just some hint for the case selection:
If you have a number of when branches with identical statements you can combine them into one branch:

e.g.:
when 10 to 14 =>
if (decipher = '1') then
key_l(0 to 27) <= key_l(26 to 27) & key_l(0 to 25);
key_r(0 to 27) <= key_r(26 to 27) & key_r(0 to 25);
else
key_l(0 to 27) <= key_l(2 to 27) & key_l(0 to 1);
key_r(0 to 27) <= key_r(2 to 27) & key_r(0 to 1);
end if;

Nonsequential selection values can be grouped using an or symbol:

like this:
when 2 | 5 | 17 => -- do something

look here for more details: http://vhdl.renerta.com/mobile/source/vhd00014.htm

Have a nice synthesis
Eilert

Andy
Guest

Wed Nov 04, 2015 6:24 pm   



Excellent suggestion.

You can define an integer subtype with the appropriate range (and a descriptive name) to use in the choice expression, or to select a slice of an array.

I use an "_range" suffix on such subtype names.

subtype active_range is integer range 10 to 14;
....
when active_range =>
....

"downto" direction also works for case choice expressions. It must match the array index direction when used to index an array.

subtype status_range is integer range 7 downto 0;
....
status := data_word(status_range);
....

You can also use such a subtype in a loop indexing scheme:

for i in status_range loop
....

Andy

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