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create 400 clocks delay for a signal

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Thomas Stanka
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Thu Jul 13, 2017 10:12 am   



Am Dienstag, 20. Juni 2017 02:25:00 UTC+2 schrieb Charles Bailey:
Quote:
Pretty much every book or manual on VHDL and logic design includes the
"wait until CLK = '1';" style as one possible way of coding clocked logic.


It is, but I bet you will find more tools not supporting this style than tools supporting it when you leave the both major simulator and synthesis tools and have to use other tools.

Additionally it is not as intuitive to understand for beginner that
wait until clk = '1' is in some cases equivalent to rising_edge(Clk) and ofc it will simulate different for clk having more states than only '1' and '0', as '1'=> 'H'=>'1' would be rising edge for your style of code.

As you are aware of this, it is fine for you, but someone else using your code will not see, if you took care of this or it is just by chance sometimes working. And it would have been no problem for you to write "wait until rising_edge(Clk)" to show other using your code what you really intended.

regards,

Thomas

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