CPLD development board with 8-bit wide Flash/EEProm

Tue Aug 17, 2010 6:08 pm   

I have a custom 8051 RTL core that I want to put into a CPLD
on a development board.

I also need an external Flash/EEProm memory on the same
CPLD development board to run 8051 code from.

Are there any CPLD EVM/development boards that come with
an 8 bit with Flash/EEProm ?

If not I, I will have to attach a socket(for the EEProm), to an
existing
CPLD board.

thanks,
-steve

Tue Aug 17, 2010 6:08 pm   

On 8/17/2010 8:08 AM, stevem1 wrote:

How many macrocells are you going to need? An 8051 is a non-trivial
amount of logic.

Meanwhile, I think that both the Altera MAX II and the Lattice MachXO
have on-chip flash that will do what you want, so you don't need to
worry about a separate chip on the EVM.

--
Rob Gaddi, Highland Technology
Email address is currently out of order

Tue Aug 17, 2010 8:14 pm   

The custom 8051 is ~10-15K std 2-input gates. That's what we get
when we put the 8051 RTL into an ASIC. But I want the 8051
programation
to be ~permanent in the CPLD and then be able to access the
external Flash/EEprom as the code memory for the 8051.
We need many of these to give to customers for 8051 code
development, but I don't want them affecting the 8051 core
programmation.
I just want them to be able to write code for the 8051 and put that
code into
an external Flash/EE, that they can program on a programmer.

It sounds like I just need to put an EEporm socket on the CPLD board.

-steve

Thu Aug 19, 2010 2:32 am   

On Aug 18, 5:14 am, stevem1 <steve.martind...@gmail.com> wrote:


I'm having trouble tracking this question.

It sounds like you sell 8051 IP, and want a 'working example', but I
cannot imagine someone doing ASICs, programming chips to flip into
sockets - they will expect a PC-Debug pathway (and usually that
pathway, can also pgm the code-storage) - your IP does have Debug,
right ?

As they are also likely going to be developing peripherals, you could
work up a Dual-FPGA platform ?
- one FPGA holds your IP and accesses the Memory, and is a stable/
known reference point, and the other holds their peripheral
developments.

A typical asic-8051 would have Flash+SRAM, and allow code to run from
either.

Interesting on an asic-8051 would be the ability to run from a
combination of SRAM + QuadSPI memory :)

-jg

Sat Aug 21, 2010 12:24 am   

Have a look at our Craignell1 http://www.enterpoint.co.uk/component_replacements/craignell.html
and Craignell2 http://www.enterpoint.co.uk/component_replacements/craignell2.html
modules. We have various processor IPs running in these.

Otherwise lots more choice in our range so if these are not what you
want have a brouse.

John Adair
Enterpoint Ltd.

On 17 Aug, 16:08, stevem1 <steve.martind...@gmail.com> wrote: